Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mediatek MT65xx Pin Controller
   8
   9 maintainers:
  10   - Sean Wang <sean.wang@kernel.org>
  11
  12 description: |+
  13   The Mediatek's Pin controller is used to control SoC pins.
  14
  15 properties:
  16   compatible:
  17     enum:
  18       - mediatek,mt2701-pinctrl
  19       - mediatek,mt2712-pinctrl
  20       - mediatek,mt6397-pinctrl
  21       - mediatek,mt7623-pinctrl
  22       - mediatek,mt8127-pinctrl
  23       - mediatek,mt8135-pinctrl
  24       - mediatek,mt8167-pinctrl
  25       - mediatek,mt8173-pinctrl
  26       - mediatek,mt8516-pinctrl
  27
  28   reg:
  29     maxItems: 1
  30
  31   pins-are-numbered:
  32     $ref: /schemas/types.yaml#/definitions/flag
  33     description: |
  34       Specify the subnodes are using numbered pinmux to specify pins.
  35
  36   gpio-controller: true
  37
  38   "#gpio-cells":
  39     const: 2
  40     description: |
  41       Number of cells in GPIO specifier. Since the generic GPIO
  42       binding is used, the amount of cells must be specified as 2. See the below
  43       mentioned gpio binding representation for description of particular cells.
  44
  45   mediatek,pctl-regmap:
  46     $ref: /schemas/types.yaml#/definitions/phandle-array
  47     items:
  48       maxItems: 1
  49     minItems: 1
  50     maxItems: 2
  51     description: |
  52       Should be phandles of the syscfg node.
  53
  54   interrupt-controller: true
  55
  56   interrupts:
  57     minItems: 1
  58     maxItems: 3
  59
  60   "#interrupt-cells":
  61     const: 2
  62
  63 required:
  64   - compatible
  65   - pins-are-numbered
  66   - gpio-controller
  67   - "#gpio-cells"
  68
  69 allOf:
  70   - $ref: "pinctrl.yaml#"
  71
  72 patternProperties:
  73   '-[0-9]+$':
  74     type: object
  75     additionalProperties: false
  76     patternProperties:
  77       'pins':
  78         type: object
  79         additionalProperties: false
  80         description: |
  81           A pinctrl node should contain at least one subnodes representing the
  82           pinctrl groups available on the machine. Each subnode will list the
  83           pins it needs, and how they should be configured, with regard to muxer
  84           configuration, pullups, drive strength, input enable/disable and input
  85           schmitt.
  86         $ref: "/schemas/pinctrl/pincfg-node.yaml"
  87
  88         properties:
  89           pinmux:
  90             description:
  91               integer array, represents gpio pin number and mux setting.
  92               Supported pin number and mux varies for different SoCs, and are
  93               defined as macros in <soc>-pinfunc.h directly.
  94
  95           bias-disable: true
  96
  97           bias-pull-up:
  98             description: |
  99               Besides generic pinconfig options, it can be used as the pull up
 100               settings for 2 pull resistors, R0 and R1. User can configure those
 101               special pins. Some macros have been defined for this usage, such
 102               as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
 103               valid arguments.
 104
 105           bias-pull-down: true
 106
 107           input-enable: true
 108
 109           input-disable: true
 110
 111           output-low: true
 112
 113           output-high: true
 114
 115           input-schmitt-enable: true
 116
 117           input-schmitt-disable: true
 118
 119           drive-strength:
 120             description: |
 121               Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
 122               etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
 123
 124         required:
 125           - pinmux
 126
 127 additionalProperties: false
 128
 129 examples:
 130   - |
 131     #include <dt-bindings/interrupt-controller/irq.h>
 132     #include <dt-bindings/interrupt-controller/arm-gic.h>
 133     #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
 134
 135     soc {
 136         #address-cells = <2>;
 137         #size-cells = <2>;
 138
 139         syscfg_pctl_a: syscfg-pctl-a@10005000 {
 140           compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
 141           reg = <0 0x10005000 0 0x1000>;
 142         };
 143
 144         syscfg_pctl_b: syscfg-pctl-b@1020c020 {
 145           compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
 146           reg = <0 0x1020C020 0 0x1000>;
 147         };
 148
 149         pinctrl@1c20800 {
 150           compatible = "mediatek,mt8135-pinctrl";
 151           reg = <0 0x1000B000 0 0x1000>;
 152           mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
 153           pins-are-numbered;
 154           gpio-controller;
 155           #gpio-cells = <2>;
 156           interrupt-controller;
 157           #interrupt-cells = <2>;
 158           interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 159               <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 160               <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 161
 162           i2c0_pins_a: i2c0-0 {
 163             pins1 {
 164               pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
 165                 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
 166               bias-disable;
 167             };
 168           };
 169
 170           i2c1_pins_a: i2c1-0 {
 171             pins {
 172               pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
 173                 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
 174               bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 175             };
 176           };
 177
 178           i2c2_pins_a: i2c2-0 {
 179             pins1 {
 180               pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
 181               bias-pull-down;
 182             };
 183
 184             pins2 {
 185               pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
 186               bias-pull-up;
 187             };
 188           };
 189
 190           i2c3_pins_a: i2c3-0 {
 191             pins1 {
 192               pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
 193                 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
 194               bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 195             };
 196
 197             pins2 {
 198               pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
 199                 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
 200               output-low;
 201               bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 202             };
 203
 204             pins3 {
 205               pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
 206                 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
 207               drive-strength = <32>;
 208             };
 209           };
 210         };
 211     };