1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Thunder Bay pin controller
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
13 Intel Thunder Bay SoC integrates a pin controller which enables control
14 of pin directions, input/output values and configuration
15 for a total of 67 pins.
19 const: intel,thunderbay-pinctrl
34 Specifies the interrupt lines to be used by the controller.
37 interrupt-controller: true
45 additionalProperties: false
48 Child nodes can be specified to contain pin configuration information,
49 which can then be utilized by pinctrl client devices.
50 The following properties are supported.
55 The name(s) of the pins to be configured in the child node.
56 Supported pin names are "GPIO0" up to "GPIO66".
65 description: Drive strength for the pad.
66 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
75 description: GPIO slew rate control.
80 additionalProperties: false
89 - interrupt-controller
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
95 #include <dt-bindings/interrupt-controller/irq.h>
98 compatible = "intel,thunderbay-pinctrl";
99 reg = <0x600b0000 0x88>;
102 gpio-ranges = <&pinctrl0 0 0 67>;
103 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
111 compatible = "intel,thunderbay-pinctrl";
112 reg = <0x600c0000 0x88>;
115 gpio-ranges = <&pinctrl1 0 0 53>;
116 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-controller;
119 #interrupt-cells = <2>;