1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16 The interface mode is selected by configuring the MII mode selection register(s)
17 (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
18 bit fields placement in SCM are different between SoCs while fields meaning
21 +-------------------------------+ |SCM |
22 | CPSW | | +---------+ |
23 | +--------------------------------+gmii_sel | |
25 | +----v---+ +--------+ | +--------------+
26 | |Port 1..<--+-->GMII/MII<------->
28 | +--------+ | +--------+ |
39 +-------------------------------+
41 CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42 CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
44 CPSW Port's Interface Mode Selection PHY device should defined as child device
45 of SCM node (scm_conf) and can be attached to each CPSW port node using standard
51 - ti,am3352-phy-gmii-sel
52 - ti,dra7xx-phy-gmii-sel
53 - ti,am43xx-phy-gmii-sel
54 - ti,dm814-phy-gmii-sel
55 - ti,am654-phy-gmii-sel
68 - ti,dra7xx-phy-gmii-sel
69 - ti,dm814-phy-gmii-sel
70 - ti,am654-phy-gmii-sel
75 description: CPSW port number (starting from 1)
81 - ti,am3352-phy-gmii-sel
82 - ti,am43xx-phy-gmii-sel
88 - CPSW port number (starting from 1)
96 additionalProperties: false
100 phy_gmii_sel: phy-gmii-sel@650 {
101 compatible = "ti,am3352-phy-gmii-sel";