1 Allwinner sun4i USB PHY
2 -----------------------
5 - compatible : should be one of
6 * allwinner,sun4i-a10-usb-phy
7 * allwinner,sun5i-a13-usb-phy
8 * allwinner,sun6i-a31-usb-phy
9 * allwinner,sun7i-a20-usb-phy
10 * allwinner,sun8i-a23-usb-phy
11 * allwinner,sun8i-a33-usb-phy
12 * allwinner,sun8i-h3-usb-phy
13 * allwinner,sun50i-a64-usb-phy
14 - reg : a list of offset + length pairs
18 * "pmu2" for sun4i, sun6i or sun7i
19 - #phy-cells : from the generic phy bindings, must be 1
20 - clocks : phandle + clock specifier for the phy clocks
22 * "usb_phy" for sun4i, sun5i or sun7i
23 * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
24 * "usb0_phy", "usb1_phy" for sun8i
25 - resets : a list of phandle + reset specifier pairs
29 * "usb2_reset" for sun4i, sun6i or sun7i
32 - usb0_id_det-gpios : gpio phandle for reading the otg id pin value
33 - usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus
34 - usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect
35 - usb0_vbus-supply : regulator phandle for controller usb0 vbus
36 - usb1_vbus-supply : regulator phandle for controller usb1 vbus
37 - usb2_vbus-supply : regulator phandle for controller usb2 vbus
40 usbphy: phy@0x01c13400 {
42 compatible = "allwinner,sun4i-a10-usb-phy";
43 /* phy base regs, phy1 pmu reg, phy2 pmu reg */
44 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
45 reg-names = "phy_ctrl", "pmu1", "pmu2";
46 clocks = <&usb_clk 8>;
47 clock-names = "usb_phy";
48 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
49 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
50 pinctrl-names = "default";
51 pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
52 usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
53 usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
54 usb0_vbus-supply = <®_usb0_vbus>;
55 usb1_vbus-supply = <®_usb1_vbus>;
56 usb2_vbus-supply = <®_usb2_vbus>;