1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY
10 - Alim Akhtar <alim.akhtar@samsung.com>
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
38 $ref: '/schemas/types.yaml#/definitions/phandle-array'
43 - description: phandle for PMU system controller interface, used to
44 control pmu registers bits for ufs m-phy
45 - description: offset of the pmu control register
47 It can be phandle/offset pair. The second cell which can represent an
64 const: samsung,exynos7-ufs-phy
70 - description: PLL reference clock
71 - description: symbol clock for input symbol (rx0-ch0 symbol clock)
72 - description: symbol clock for input symbol (rx1-ch1 symbol clock)
73 - description: symbol clock for output symbol (tx0 symbol clock)
78 - const: rx1_symbol_clk
79 - const: rx0_symbol_clk
80 - const: tx0_symbol_clk
86 - description: PLL reference clock
92 additionalProperties: false
96 #include <dt-bindings/clock/exynos7-clk.h>
98 ufs_phy: ufs-phy@15571800 {
99 compatible = "samsung,exynos7-ufs-phy";
100 reg = <0x15571800 0x240>;
101 reg-names = "phy-pma";
102 samsung,pmu-syscon = <&pmu_system_controller>;
104 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
105 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
106 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
107 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
108 clock-names = "ref_clk", "rx1_symbol_clk",
109 "rx0_symbol_clk", "tx0_symbol_clk";