Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
   8
   9 maintainers:
  10   - Heiko Stuebner <heiko@sntech.de>
  11
  12 properties:
  13   "#phy-cells":
  14     const: 0
  15
  16   compatible:
  17     enum:
  18       - rockchip,px30-dsi-dphy
  19       - rockchip,rk3128-dsi-dphy
  20       - rockchip,rk3368-dsi-dphy
  21       - rockchip,rk3568-dsi-dphy
  22       - rockchip,rv1126-dsi-dphy
  23
  24   reg:
  25     maxItems: 1
  26
  27   clocks:
  28     items:
  29       - description: PLL reference clock
  30       - description: Module clock
  31
  32   clock-names:
  33     items:
  34       - const: ref
  35       - const: pclk
  36
  37   power-domains:
  38     maxItems: 1
  39     description: phandle to the associated power domain
  40
  41   resets:
  42     items:
  43       - description: exclusive PHY reset line
  44
  45   reset-names:
  46     items:
  47       - const: apb
  48
  49 required:
  50   - "#phy-cells"
  51   - compatible
  52   - reg
  53   - clocks
  54   - clock-names
  55   - resets
  56   - reset-names
  57
  58 additionalProperties: false
  59
  60 examples:
  61   - |
  62     dsi_dphy: phy@ff2e0000 {
  63         compatible = "rockchip,px30-dsi-dphy";
  64         reg = <0xff2e0000 0x10000>;
  65         clocks = <&pmucru 13>, <&cru 12>;
  66         clock-names = "ref", "pclk";
  67         resets = <&cru 12>;
  68         reset-names = "apb";
  69         #phy-cells = <0>;
  70     };
  71
  72 ...