Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip PCIe v3 phy
   8
   9 maintainers:
  10   - Heiko Stuebner <heiko@sntech.de>
  11
  12 properties:
  13   compatible:
  14     enum:
  15       - rockchip,rk3568-pcie3-phy
  16       - rockchip,rk3588-pcie3-phy
  17
  18   reg:
  19     maxItems: 1
  20
  21   clocks:
  22     minItems: 1
  23     maxItems: 3
  24
  25   clock-names:
  26     minItems: 1
  27     maxItems: 3
  28
  29   data-lanes:
  30     description: which lanes (by position) should be mapped to which
  31       controller (value). 0 means lane disabled, higher value means used.
  32       (controller-number +1 )
  33     $ref: /schemas/types.yaml#/definitions/uint32-array
  34     minItems: 2
  35     maxItems: 16
  36     items:
  37       minimum: 0
  38       maximum: 16
  39
  40   "#phy-cells":
  41     const: 0
  42
  43   resets:
  44     maxItems: 1
  45
  46   reset-names:
  47     const: phy
  48
  49   rockchip,phy-grf:
  50     $ref: /schemas/types.yaml#/definitions/phandle
  51     description: phandle to the syscon managing the phy "general register files"
  52
  53   rockchip,pipe-grf:
  54     $ref: /schemas/types.yaml#/definitions/phandle
  55     description: phandle to the syscon managing the pipe "general register files"
  56
  57 required:
  58   - compatible
  59   - reg
  60   - rockchip,phy-grf
  61   - "#phy-cells"
  62
  63 allOf:
  64   - if:
  65       properties:
  66         compatible:
  67           enum:
  68             - rockchip,rk3588-pcie3-phy
  69     then:
  70       properties:
  71         clocks:
  72           maxItems: 1
  73         clock-names:
  74           items:
  75             - const: pclk
  76     else:
  77       properties:
  78         clocks:
  79           minItems: 3
  80
  81         clock-names:
  82           items:
  83             - const: refclk_m
  84             - const: refclk_n
  85             - const: pclk
  86
  87 additionalProperties: false
  88
  89 examples:
  90   - |
  91     #include <dt-bindings/clock/rk3568-cru.h>
  92     pcie30phy: phy@fe8c0000 {
  93       compatible = "rockchip,rk3568-pcie3-phy";
  94       reg = <0xfe8c0000 0x20000>;
  95       #phy-cells = <0>;
  96       clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
  97                <&pmucru CLK_PCIE30PHY_REF_N>,
  98                <&cru PCLK_PCIE30PHY>;
  99       clock-names = "refclk_m", "refclk_n", "pclk";
 100       resets = <&cru SRST_PCIE30PHY>;
 101       reset-names = "phy";
 102       rockchip,phy-grf = <&pcie30_phy_grf>;
 103     };