1 Qualcomm QMP PHY controller
2 ===========================
4 QMP phy controller supports physical layer functionality for a number of
5 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
13 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
16 - For "qcom,sdm845-qmp-usb3-phy":
17 - index 0: address and length of register set for PHY's common serdes
19 - named register "dp_com" (using reg-names): address and length of the
22 - offset and length of register set for PHY's common serdes block.
24 - #clock-cells: must be 1
25 - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
26 interface (for pipe based PHYs). These clock are then gate-controlled
28 - #address-cells: must be 1
29 - #size-cells: must be 1
30 - ranges: must be present
32 - clocks: a list of phandles and clock-specifier pairs,
33 one for each entry in clock-names.
34 - clock-names: "cfg_ahb" for phy config clock,
35 "aux" for phy aux clock,
36 "ref" for 19.2 MHz ref clk,
37 "com_aux" for phy common block aux clock,
38 For "qcom,msm8996-qmp-pcie-phy" must contain:
39 "aux", "cfg_ahb", "ref".
40 For "qcom,msm8996-qmp-usb3-phy" must contain:
41 "aux", "cfg_ahb", "ref".
42 For "qcom,qmp-v3-usb3-phy" must contain:
43 "aux", "cfg_ahb", "ref", "com_aux".
45 - resets: a list of phandles and reset controller specifier pairs,
46 one for each entry in reset-names.
47 - reset-names: "phy" for reset of phy block,
48 "common" for phy common block reset,
49 "cfg" for phy's ahb cfg block reset (Optional).
50 For "qcom,msm8996-qmp-pcie-phy" must contain:
51 "phy", "common", "cfg".
52 For "qcom,msm8996-qmp-usb3-phy" must contain
54 For "qcom,ipq8074-qmp-pcie-phy" must contain:
57 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
58 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
61 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
65 - Each device node of QMP phy is required to have as many child nodes as
66 the number of lanes the PHY has.
68 Required properties for child node:
69 - reg: list of offset and length pairs of register sets for PHY blocks -
73 - index 3: pcs_misc (optional)
75 - #phy-cells: must be 0
77 - clocks: a list of phandles and clock-specifier pairs,
78 one for each entry in clock-names.
79 - clock-names: Must contain following for pcie and usb qmp phys:
80 "pipe<lane-number>" for pipe clock specific to each lane.
81 - clock-output-names: Name of the PHY clock that will be the parent for
84 For "qcom,ipq8074-qmp-pcie-phy":
85 - "pcie20_phy0_pipe_clk" Pipe Clock parent
87 "pcie20_phy1_pipe_clk"
89 - resets: a list of phandles and reset controller specifier pairs,
90 one for each entry in reset-names.
91 - reset-names: Must contain following for pcie qmp phys:
92 "lane<lane-number>" for reset specific to each lane.
96 compatible = "qcom,msm8996-qmp-pcie-phy";
97 reg = <0x34000 0x488>;
103 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
104 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
105 <&gcc GCC_PCIE_CLKREF_CLK>;
106 clock-names = "aux", "cfg_ahb", "ref";
108 vdda-phy-supply = <&pm8994_l28>;
109 vdda-pll-supply = <&pm8994_l12>;
111 resets = <&gcc GCC_PCIE_PHY_BCR>,
112 <&gcc GCC_PCIE_PHY_COM_BCR>,
113 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
114 reset-names = "phy", "common", "cfg";
116 pciephy_0: lane@35000 {
117 reg = <0x35000 0x130>,
122 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
123 clock-names = "pipe0";
124 clock-output-names = "pcie_0_pipe_clk_src";
125 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
126 reset-names = "lane0";
129 pciephy_1: lane@36000 {