Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description:
  13   The QMP PHY controller supports physical layer functionality for a number of
  14   controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - qcom,sa8775p-qmp-gen4x2-pcie-phy
  20       - qcom,sa8775p-qmp-gen4x4-pcie-phy
  21       - qcom,sc8180x-qmp-pcie-phy
  22       - qcom,sc8280xp-qmp-gen3x1-pcie-phy
  23       - qcom,sc8280xp-qmp-gen3x2-pcie-phy
  24       - qcom,sc8280xp-qmp-gen3x4-pcie-phy
  25       - qcom,sdm845-qhp-pcie-phy
  26       - qcom,sdm845-qmp-pcie-phy
  27       - qcom,sdx55-qmp-pcie-phy
  28       - qcom,sdx65-qmp-gen4x2-pcie-phy
  29       - qcom,sm8150-qmp-gen3x1-pcie-phy
  30       - qcom,sm8150-qmp-gen3x2-pcie-phy
  31       - qcom,sm8250-qmp-gen3x1-pcie-phy
  32       - qcom,sm8250-qmp-gen3x2-pcie-phy
  33       - qcom,sm8250-qmp-modem-pcie-phy
  34       - qcom,sm8350-qmp-gen3x1-pcie-phy
  35       - qcom,sm8450-qmp-gen3x1-pcie-phy
  36       - qcom,sm8450-qmp-gen4x2-pcie-phy
  37       - qcom,sm8550-qmp-gen3x2-pcie-phy
  38       - qcom,sm8550-qmp-gen4x2-pcie-phy
  39
  40   reg:
  41     minItems: 1
  42     maxItems: 2
  43
  44   clocks:
  45     minItems: 5
  46     maxItems: 7
  47
  48   clock-names:
  49     minItems: 5
  50     items:
  51       - const: aux
  52       - const: cfg_ahb
  53       - const: ref
  54       - enum: [rchng, refgen]
  55       - const: pipe
  56       - const: pipediv2
  57       - const: phy_aux
  58
  59   power-domains:
  60     maxItems: 1
  61
  62   resets:
  63     minItems: 1
  64     maxItems: 2
  65
  66   reset-names:
  67     minItems: 1
  68     items:
  69       - const: phy
  70       - const: phy_nocsr
  71
  72   vdda-phy-supply: true
  73
  74   vdda-pll-supply: true
  75
  76   vdda-qref-supply: true
  77
  78   qcom,4ln-config-sel:
  79     description: PCIe 4-lane configuration
  80     $ref: /schemas/types.yaml#/definitions/phandle-array
  81     items:
  82       - items:
  83           - description: phandle of TCSR syscon
  84           - description: offset of PCIe 4-lane configuration register
  85           - description: offset of configuration bit for this PHY
  86
  87   "#clock-cells":
  88     const: 0
  89
  90   clock-output-names:
  91     maxItems: 1
  92
  93   "#phy-cells":
  94     const: 0
  95
  96 required:
  97   - compatible
  98   - reg
  99   - clocks
 100   - clock-names
 101   - resets
 102   - reset-names
 103   - vdda-phy-supply
 104   - vdda-pll-supply
 105   - "#clock-cells"
 106   - clock-output-names
 107   - "#phy-cells"
 108
 109 additionalProperties: false
 110
 111 allOf:
 112   - if:
 113       properties:
 114         compatible:
 115           contains:
 116             enum:
 117               - qcom,sc8280xp-qmp-gen3x4-pcie-phy
 118     then:
 119       properties:
 120         reg:
 121           items:
 122             - description: port a
 123             - description: port b
 124       required:
 125         - qcom,4ln-config-sel
 126     else:
 127       properties:
 128         reg:
 129           maxItems: 1
 130
 131   - if:
 132       properties:
 133         compatible:
 134           contains:
 135             enum:
 136               - qcom,sc8180x-qmp-pcie-phy
 137               - qcom,sdm845-qhp-pcie-phy
 138               - qcom,sdm845-qmp-pcie-phy
 139               - qcom,sdx55-qmp-pcie-phy
 140               - qcom,sm8150-qmp-gen3x1-pcie-phy
 141               - qcom,sm8150-qmp-gen3x2-pcie-phy
 142               - qcom,sm8250-qmp-gen3x1-pcie-phy
 143               - qcom,sm8250-qmp-gen3x2-pcie-phy
 144               - qcom,sm8250-qmp-modem-pcie-phy
 145               - qcom,sm8350-qmp-gen3x1-pcie-phy
 146               - qcom,sm8450-qmp-gen3x1-pcie-phy
 147               - qcom,sm8450-qmp-gen3x2-pcie-phy
 148               - qcom,sm8550-qmp-gen3x2-pcie-phy
 149               - qcom,sm8550-qmp-gen4x2-pcie-phy
 150     then:
 151       properties:
 152         clocks:
 153           maxItems: 5
 154         clock-names:
 155           maxItems: 5
 156
 157   - if:
 158       properties:
 159         compatible:
 160           contains:
 161             enum:
 162               - qcom,sc8280xp-qmp-gen3x1-pcie-phy
 163               - qcom,sc8280xp-qmp-gen3x2-pcie-phy
 164               - qcom,sc8280xp-qmp-gen3x4-pcie-phy
 165     then:
 166       properties:
 167         clocks:
 168           minItems: 6
 169         clock-names:
 170           minItems: 6
 171
 172   - if:
 173       properties:
 174         compatible:
 175           contains:
 176             enum:
 177               - qcom,sa8775p-qmp-gen4x2-pcie-phy
 178               - qcom,sa8775p-qmp-gen4x4-pcie-phy
 179     then:
 180       properties:
 181         clocks:
 182           minItems: 7
 183         clock-names:
 184           minItems: 7
 185
 186   - if:
 187       properties:
 188         compatible:
 189           contains:
 190             enum:
 191               - qcom,sm8550-qmp-gen4x2-pcie-phy
 192     then:
 193       properties:
 194         resets:
 195           minItems: 2
 196         reset-names:
 197           minItems: 2
 198     else:
 199       properties:
 200         resets:
 201           maxItems: 1
 202         reset-names:
 203           maxItems: 1
 204
 205 examples:
 206   - |
 207     #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
 208
 209     pcie2b_phy: phy@1c18000 {
 210       compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
 211       reg = <0x01c18000 0x2000>;
 212
 213       clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
 214                <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
 215                <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
 216                <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
 217                <&gcc GCC_PCIE_2B_PIPE_CLK>,
 218                <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
 219       clock-names = "aux", "cfg_ahb", "ref", "rchng",
 220                     "pipe", "pipediv2";
 221
 222       power-domains = <&gcc PCIE_2B_GDSC>;
 223
 224       resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
 225       reset-names = "phy";
 226
 227       vdda-phy-supply = <&vreg_l6d>;
 228       vdda-pll-supply = <&vreg_l4d>;
 229
 230       #clock-cells = <0>;
 231       clock-output-names = "pcie_2b_pipe_clk";
 232
 233       #phy-cells = <0>;
 234     };
 235
 236     pcie2a_phy: phy@1c24000 {
 237       compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
 238       reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
 239
 240       clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
 241                <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
 242                <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
 243                <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
 244                <&gcc GCC_PCIE_2A_PIPE_CLK>,
 245                <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
 246       clock-names = "aux", "cfg_ahb", "ref", "rchng",
 247                     "pipe", "pipediv2";
 248
 249       power-domains = <&gcc PCIE_2A_GDSC>;
 250
 251       resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
 252       reset-names = "phy";
 253
 254       vdda-phy-supply = <&vreg_l6d>;
 255       vdda-pll-supply = <&vreg_l4d>;
 256
 257       qcom,4ln-config-sel = <&tcsr 0xa044 0>;
 258
 259       #clock-cells = <0>;
 260       clock-output-names = "pcie_2a_pipe_clk";
 261
 262       #phy-cells = <0>;
 263     };