1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QUSB2 phy controller
11 - Wesley Cheng <quic_wcheng@quicinc.com>
14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8953-qusb2-phy
23 - qcom,msm8996-qusb2-phy
24 - qcom,msm8998-qusb2-phy
25 - qcom,qcm2290-qusb2-phy
26 - qcom,sdm660-qusb2-phy
27 - qcom,ipq6018-qusb2-phy
28 - qcom,sm4250-qusb2-phy
29 - qcom,sm6115-qusb2-phy
32 - qcom,sc7180-qusb2-phy
33 - qcom,sdm670-qusb2-phy
34 - qcom,sdm845-qusb2-phy
35 - qcom,sm6350-qusb2-phy
36 - const: qcom,qusb2-v2-phy
46 - description: phy config clock
47 - description: 19.2 MHz ref clk
48 - description: phy interface clock (Optional)
59 Phandle to 0.9V regulator supply to PHY digital circuit.
63 Phandle to 1.8V regulator supply to PHY refclk pll block.
67 Phandle to 3.1V regulator supply to Dp/Dm port signals.
72 Phandle to reset to phy block.
77 Phandle to nvmem cell that contains 'HS Tx trim'
78 tuning parameter value for qusb2 phy.
82 Phandle to TCSR syscon register region.
83 $ref: /schemas/types.yaml#/definitions/phandle
89 const: qcom,qusb2-v2-phy
92 qcom,imp-res-offset-value:
94 It is a 6 bit value that specifies offset to be
95 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
96 tuning parameter that may vary for different boards of same SOC.
97 $ref: /schemas/types.yaml#/definitions/uint32
102 qcom,bias-ctrl-value:
104 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
105 tuning parameter that may vary for different boards of same SOC.
106 $ref: /schemas/types.yaml#/definitions/uint32
111 qcom,charge-ctrl-value:
113 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
114 tuning parameter that may vary for different boards of same SOC.
115 $ref: /schemas/types.yaml#/definitions/uint32
120 qcom,hstx-trim-value:
122 It is a 4 bit value that specifies tuning for HSTX
124 Possible range is - 15mA to 24mA (stepsize of 600 uA).
125 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
126 $ref: /schemas/types.yaml#/definitions/uint32
131 qcom,preemphasis-level:
133 It is a 2 bit value that specifies pre-emphasis level.
134 Possible range is 0 to 15% (stepsize of 5%).
135 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
136 $ref: /schemas/types.yaml#/definitions/uint32
141 qcom,preemphasis-width:
143 It is a 1 bit value that specifies how long the HSTX
144 pre-emphasis (specified using qcom,preemphasis-level) must be in
145 effect. Duration could be half-bit of full-bit.
146 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
147 $ref: /schemas/types.yaml#/definitions/uint32
152 qcom,hsdisc-trim-value:
154 It is a 2 bit value tuning parameter that control disconnect
155 threshold and may vary for different boards of same SOC.
156 $ref: /schemas/types.yaml#/definitions/uint32
169 - vdda-phy-dpdm-supply
172 additionalProperties: false
176 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
177 hsusb_phy: phy@7411000 {
178 compatible = "qcom,msm8996-qusb2-phy";
179 reg = <0x7411000 0x180>;
182 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
183 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
184 clock-names = "cfg_ahb", "ref";
186 vdd-supply = <&pm8994_l28>;
187 vdda-pll-supply = <&pm8994_l12>;
188 vdda-phy-dpdm-supply = <&pm8994_l24>;
190 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
191 nvmem-cells = <&qusb2p_hstx_trim>;