Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm QMP PHY controller (UFS)
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description:
  13   QMP PHY controller supports physical layer functionality for a number of
  14   controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - qcom,msm8996-qmp-ufs-phy
  20       - qcom,msm8998-qmp-ufs-phy
  21       - qcom,sc8180x-qmp-ufs-phy
  22       - qcom,sc8280xp-qmp-ufs-phy
  23       - qcom,sdm845-qmp-ufs-phy
  24       - qcom,sm6115-qmp-ufs-phy
  25       - qcom,sm6350-qmp-ufs-phy
  26       - qcom,sm8150-qmp-ufs-phy
  27       - qcom,sm8250-qmp-ufs-phy
  28       - qcom,sm8350-qmp-ufs-phy
  29       - qcom,sm8450-qmp-ufs-phy
  30
  31   reg:
  32     items:
  33       - description: serdes
  34
  35   "#address-cells":
  36     enum: [ 1, 2 ]
  37
  38   "#size-cells":
  39     enum: [ 1, 2 ]
  40
  41   ranges: true
  42
  43   clocks:
  44     minItems: 1
  45     maxItems: 3
  46
  47   clock-names:
  48     minItems: 1
  49     maxItems: 3
  50
  51   power-domains:
  52     maxItems: 1
  53
  54   resets:
  55     maxItems: 1
  56
  57   reset-names:
  58     items:
  59       - const: ufsphy
  60
  61   vdda-phy-supply: true
  62
  63   vdda-pll-supply: true
  64
  65   vddp-ref-clk-supply: true
  66
  67 patternProperties:
  68   "^phy@[0-9a-f]+$":
  69     type: object
  70     description: single PHY-provider child node
  71     properties:
  72       reg:
  73         minItems: 3
  74         maxItems: 6
  75
  76       "#phy-cells":
  77         const: 0
  78
  79     required:
  80       - reg
  81       - "#phy-cells"
  82
  83     additionalProperties: false
  84
  85 required:
  86   - compatible
  87   - reg
  88   - "#address-cells"
  89   - "#size-cells"
  90   - ranges
  91   - clocks
  92   - clock-names
  93   - resets
  94   - reset-names
  95   - vdda-phy-supply
  96   - vdda-pll-supply
  97
  98 additionalProperties: false
  99
 100 allOf:
 101   - if:
 102       properties:
 103         compatible:
 104           contains:
 105             enum:
 106               - qcom,msm8996-qmp-ufs-phy
 107     then:
 108       properties:
 109         clocks:
 110           maxItems: 1
 111         clock-names:
 112           items:
 113             - const: ref
 114
 115   - if:
 116       properties:
 117         compatible:
 118           contains:
 119             enum:
 120               - qcom,msm8998-qmp-ufs-phy
 121               - qcom,sc8180x-qmp-ufs-phy
 122               - qcom,sc8280xp-qmp-ufs-phy
 123               - qcom,sdm845-qmp-ufs-phy
 124               - qcom,sm6115-qmp-ufs-phy
 125               - qcom,sm6350-qmp-ufs-phy
 126               - qcom,sm8150-qmp-ufs-phy
 127               - qcom,sm8250-qmp-ufs-phy
 128     then:
 129       properties:
 130         clocks:
 131           maxItems: 2
 132         clock-names:
 133           items:
 134             - const: ref
 135             - const: ref_aux
 136
 137   - if:
 138       properties:
 139         compatible:
 140           contains:
 141             enum:
 142               - qcom,sm8450-qmp-ufs-phy
 143     then:
 144       properties:
 145         clocks:
 146           maxItems: 3
 147         clock-names:
 148           items:
 149             - const: ref
 150             - const: ref_aux
 151             - const: qref
 152
 153   - if:
 154       properties:
 155         compatible:
 156           contains:
 157             enum:
 158               - qcom,msm8998-qmp-ufs-phy
 159               - qcom,sc8280xp-qmp-ufs-phy
 160               - qcom,sdm845-qmp-ufs-phy
 161               - qcom,sm6350-qmp-ufs-phy
 162               - qcom,sm8150-qmp-ufs-phy
 163               - qcom,sm8250-qmp-ufs-phy
 164               - qcom,sm8350-qmp-ufs-phy
 165               - qcom,sm8450-qmp-ufs-phy
 166     then:
 167       patternProperties:
 168         "^phy@[0-9a-f]+$":
 169           properties:
 170             reg:
 171               items:
 172                 - description: TX lane 1
 173                 - description: RX lane 1
 174                 - description: PCS
 175                 - description: TX lane 2
 176                 - description: RX lane 2
 177
 178   - if:
 179       properties:
 180         compatible:
 181           contains:
 182             enum:
 183               - qcom,sc8180x-qmp-ufs-phy
 184     then:
 185       patternProperties:
 186         "^phy@[0-9a-f]+$":
 187           properties:
 188             reg:
 189               items:
 190                 - description: TX
 191                 - description: RX
 192                 - description: PCS
 193                 - description: PCS_MISC
 194
 195   - if:
 196       properties:
 197         compatible:
 198           contains:
 199             enum:
 200               - qcom,msm8996-qmp-ufs-phy
 201               - qcom,sm6115-qmp-ufs-phy
 202     then:
 203       patternProperties:
 204         "^phy@[0-9a-f]+$":
 205           properties:
 206             reg:
 207               items:
 208                 - description: TX
 209                 - description: RX
 210                 - description: PCS
 211
 212 examples:
 213   - |
 214     #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
 215     #include <dt-bindings/clock/qcom,rpmh.h>
 216     phy-wrapper@1d87000 {
 217         compatible = "qcom,sc8280xp-qmp-ufs-phy";
 218         reg = <0x01d87000 0xe10>;
 219         #address-cells = <1>;
 220         #size-cells = <1>;
 221         ranges = <0x0 0x01d87000 0x1000>;
 222
 223         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 224         clock-names = "ref", "ref_aux";
 225
 226         resets = <&ufs_mem_hc 0>;
 227         reset-names = "ufsphy";
 228
 229         vdda-phy-supply = <&vreg_l6b>;
 230         vdda-pll-supply = <&vreg_l3b>;
 231
 232         phy@400 {
 233             reg = <0x400 0x108>,
 234                   <0x600 0x1e0>,
 235                   <0xc00 0x1dc>,
 236                   <0x800 0x108>,
 237                   <0xa00 0x1e0>;
 238             #phy-cells = <0>;
 239         };
 240     };