1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,msm8998-qmp-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
24 - qcom,sdm845-qhp-pcie-phy
25 - qcom,sdm845-qmp-pcie-phy
26 - qcom,sdx55-qmp-pcie-phy
27 - qcom,sm8250-qmp-gen3x1-pcie-phy
28 - qcom,sm8250-qmp-gen3x2-pcie-phy
29 - qcom,sm8250-qmp-modem-pcie-phy
30 - qcom,sm8450-qmp-gen3x1-pcie-phy
31 - qcom,sm8450-qmp-gen4x2-pcie-phy
65 vddp-ref-clk-supply: true
70 description: single PHY-provider child node
78 - description: PIPE clock
101 additionalProperties: false
114 additionalProperties: false
122 - qcom,msm8998-qmp-pcie-phy
147 - qcom,ipq6018-qmp-pcie-phy
148 - qcom,ipq8074-qmp-gen3-pcie-phy
149 - qcom,ipq8074-qmp-pcie-phy
170 - qcom,sc8180x-qmp-pcie-phy
171 - qcom,sdm845-qhp-pcie-phy
172 - qcom,sdm845-qmp-pcie-phy
173 - qcom,sdx55-qmp-pcie-phy
174 - qcom,sm8250-qmp-gen3x1-pcie-phy
175 - qcom,sm8250-qmp-gen3x2-pcie-phy
176 - qcom,sm8250-qmp-modem-pcie-phy
177 - qcom,sm8450-qmp-gen3x1-pcie-phy
178 - qcom,sm8450-qmp-gen4x2-pcie-phy
203 - qcom,sm8250-qmp-gen3x2-pcie-phy
204 - qcom,sm8250-qmp-modem-pcie-phy
205 - qcom,sm8450-qmp-gen4x2-pcie-phy
212 - description: TX lane 1
213 - description: RX lane 1
215 - description: TX lane 2
216 - description: RX lane 2
217 - description: PCS_MISC
224 - qcom,sc8180x-qmp-pcie-phy
225 - qcom,sdm845-qmp-pcie-phy
226 - qcom,sdx55-qmp-pcie-phy
227 - qcom,sm8250-qmp-gen3x1-pcie-phy
228 - qcom,sm8450-qmp-gen3x1-pcie-phy
238 - description: PCS_MISC
245 - qcom,ipq6018-qmp-pcie-phy
246 - qcom,ipq8074-qmp-pcie-phy
247 - qcom,msm8998-qmp-pcie-phy
248 - qcom,sdm845-qhp-pcie-phy
261 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
262 phy-wrapper@1c0e000 {
263 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
264 reg = <0x01c0e000 0x1c0>;
265 #address-cells = <1>;
267 ranges = <0x0 0x01c0e000 0x1000>;
269 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
270 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
271 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
272 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
273 clock-names = "aux", "cfg_ahb", "ref", "refgen";
275 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
278 vdda-phy-supply = <&vreg_l10c_0p88>;
279 vdda-pll-supply = <&vreg_l6b_1p2>;
289 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
292 clock-output-names = "pcie_1_pipe_clk";