1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (MSM8996 PCIe)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
18 const: qcom,msm8996-qmp-pcie-phy
54 vddp-ref-clk-supply: true
59 description: one child node per PHY provided by this block
69 - description: PIPE clock
81 - description: PHY reset
108 additionalProperties: false
123 additionalProperties: false
127 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
128 pcie_phy: phy-wrapper@34000 {
129 compatible = "qcom,msm8996-qmp-pcie-phy";
130 reg = <0x34000 0x488>;
131 #address-cells = <1>;
133 ranges = <0x0 0x34000 0x4000>;
135 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
136 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
137 <&gcc GCC_PCIE_CLKREF_CLK>;
138 clock-names = "aux", "cfg_ahb", "ref";
140 resets = <&gcc GCC_PCIE_PHY_BCR>,
141 <&gcc GCC_PCIE_PHY_COM_BCR>,
142 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
143 reset-names = "phy", "common", "cfg";
145 vdda-phy-supply = <&vreg_l28a_0p925>;
146 vdda-pll-supply = <&vreg_l12a_1p8>;
148 pciephy_0: phy@1000 {
149 reg = <0x1000 0x130>,
153 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
154 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
157 clock-output-names = "pcie_0_pipe_clk_src";
162 pciephy_1: phy@2000 {
163 reg = <0x2000 0x130>,
167 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
168 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
171 clock-output-names = "pcie_1_pipe_clk_src";
176 pciephy_2: phy@3000 {
177 reg = <0x3000 0x130>,
181 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
182 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
185 clock-output-names = "pcie_2_pipe_clk_src";