1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
22 - description: reference clock
23 - description: apb clock
24 - description: pipe clock
34 - description: exclusive PHY reset line
39 The option SSC can be enabled for U3, SATA and PCIE.
40 Most commercially available platforms use SSC to reduce EMI.
45 Many PCIe connections, especially backplane connections,
46 require a synchronous reference clock between the two link partners.
47 To achieve this a common clock source, referred to as REFCLK in
48 the PCI Express Card Electromechanical Specification,
49 should be used by both ends of the PCIe link.
50 In PCIe mode one can choose to use an internal or an external reference
52 By default the internal clock is selected. The PCIe PHY provides a 100MHz
53 differential clock output(optional with SSC) for system applications.
54 When selecting this option an externally 100MHz differential
55 reference clock needs to be provided to the PCIe PHY.
58 $ref: /schemas/types.yaml#/definitions/phandle
60 Some additional phy settings are accessed through GRF regs.
62 rockchip,pipe-phy-grf:
63 $ref: /schemas/types.yaml#/definitions/phandle
65 Some additional pipe settings are accessed through GRF regs.
77 - rockchip,pipe-phy-grf
80 additionalProperties: false
84 #include <dt-bindings/clock/rk3568-cru.h>
86 pipegrf: syscon@fdc50000 {
87 compatible = "rockchip,rk3568-pipe-grf", "syscon";
88 reg = <0xfdc50000 0x1000>;
91 pipe_phy_grf0: syscon@fdc70000 {
92 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
93 reg = <0xfdc70000 0x1000>;
96 combphy0: phy@fe820000 {
97 compatible = "rockchip,rk3568-naneng-combphy";
98 reg = <0xfe820000 0x100>;
99 clocks = <&pmucru CLK_PCIEPHY0_REF>,
100 <&cru PCLK_PIPEPHY0>,
102 clock-names = "ref", "apb", "pipe";
103 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
104 assigned-clock-rates = <100000000>;
105 resets = <&cru SRST_PIPEPHY0>;
106 rockchip,pipe-grf = <&pipegrf>;
107 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;