1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Torrent SD0801 PHY binding
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
12 PHY also supports multilink multiprotocol combinations including protocols
13 such as PCIe, USB, SGMII, QSGMII etc.
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
38 PHY reference clock for 1 item. Must contain an entry in clock-names.
39 Optional Parent to enable output reference clock.
45 - const: phy_en_refclk
50 assigned-clock-parents:
56 - description: Offset of the Torrent PHY configuration registers.
57 - description: Offset of the DPTX PHY configuration registers.
68 - description: Torrent PHY reset.
69 - description: Torrent APB reset. This is optional.
74 - const: torrent_reset
81 Each group of PHY lanes with a single master lane should be represented as a sub-node.
85 The master lane number. This is the lowest numbered lane in the lane group.
93 Contains list of resets, one per lane, to get all the link lanes out of reset.
100 Specifies the type of PHY for which the group of PHY lanes is used.
101 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
102 $ref: /schemas/types.yaml#/definitions/uint32
109 $ref: /schemas/types.yaml#/definitions/uint32
115 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
116 EXTERNAL_SSC or INTERNAL_SSC.
117 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
118 $ref: /schemas/types.yaml#/definitions/uint32
124 Maximum DisplayPort link bit rate to use, in Mbps
125 $ref: /schemas/types.yaml#/definitions/uint32
126 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
136 additionalProperties: false
149 additionalProperties: false
153 #include <dt-bindings/phy/phy.h>
156 #address-cells = <2>;
159 torrent-phy@f0fb500000 {
160 compatible = "cdns,torrent-phy";
161 reg = <0xf0 0xfb500000 0x0 0x00100000>,
162 <0xf0 0xfb030a00 0x0 0x00000040>;
163 reg-names = "torrent_phy", "dptx_phy";
164 resets = <&phyrst 0>;
165 reset-names = "torrent_reset";
167 clock-names = "refclk";
168 #address-cells = <1>;
172 resets = <&phyrst 1>, <&phyrst 2>,
173 <&phyrst 3>, <&phyrst 4>;
175 cdns,phy-type = <PHY_TYPE_DP>;
176 cdns,num-lanes = <4>;
177 cdns,max-bit-rate = <8100>;
182 #include <dt-bindings/phy/phy.h>
183 #include <dt-bindings/phy/phy-cadence.h>
186 #address-cells = <2>;
189 torrent-phy@f0fb500000 {
190 compatible = "cdns,torrent-phy";
191 reg = <0xf0 0xfb500000 0x0 0x00100000>;
192 reg-names = "torrent_phy";
193 resets = <&phyrst 0>, <&phyrst 1>;
194 reset-names = "torrent_reset", "torrent_apb";
196 clock-names = "refclk";
197 #address-cells = <1>;
201 resets = <&phyrst 2>, <&phyrst 3>;
203 cdns,phy-type = <PHY_TYPE_PCIE>;
204 cdns,num-lanes = <2>;
205 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
210 resets = <&phyrst 4>;
212 cdns,phy-type = <PHY_TYPE_SGMII>;
213 cdns,num-lanes = <1>;
214 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;