1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Sierra PHY binding
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
11 multiprotocol combinations including protocols such as PCIe, USB etc.
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
35 - description: Sierra PHY reset.
36 - description: Sierra APB reset. This is optional.
47 Offset of the Sierra PHY configuration registers.
59 - const: cmn_refclk_dig_div
60 - const: cmn_refclk1_dig_div
68 assigned-clock-parents:
75 A boolean property whose presence indicates that the PHY registers will be
76 configured by hardware. If not present, all sub-node optional properties
83 Each group of PHY lanes with a single master lane should be represented as
84 a sub-node. Note that the actual configuration of each lane is determined
85 by hardware strapping, and must match the configuration specified here.
89 The master lane number. This is the lowest numbered lane in the lane group.
97 Contains list of resets, one per lane, to get all the link lanes out of reset.
104 Specifies the type of PHY for which the group of PHY lanes is used.
105 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
106 $ref: /schemas/types.yaml#/definitions/uint32
111 Number of lanes in this group. The group is made up of consecutive lanes.
112 $ref: /schemas/types.yaml#/definitions/uint32
118 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
119 EXTERNAL_SSC or INTERNAL_SSC.
120 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
121 $ref: /schemas/types.yaml#/definitions/uint32
130 additionalProperties: false
140 additionalProperties: false
144 #include <dt-bindings/phy/phy.h>
147 #address-cells = <2>;
150 sierra-phy@fd240000 {
151 compatible = "cdns,sierra-phy-t0";
152 reg = <0x0 0xfd240000 0x0 0x40000>;
153 resets = <&phyrst 0>, <&phyrst 1>;
154 reset-names = "sierra_reset", "sierra_apb";
155 clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
156 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
157 #address-cells = <1>;
161 resets = <&phyrst 2>;
162 cdns,num-lanes = <2>;
164 cdns,phy-type = <PHY_TYPE_PCIE>;
168 resets = <&phyrst 4>;
169 cdns,num-lanes = <1>;
171 cdns,phy-type = <PHY_TYPE_PCIE>;