1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
19 - nvidia,tegra124-usb-phy
20 - nvidia,tegra114-usb-phy
22 - nvidia,tegra30-usb-phy
25 - nvidia,tegra30-usb-phy
26 - nvidia,tegra20-usb-phy
32 PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
33 PHY0 and PHY2 must specify two register sets, where the first set is
34 PHY own registers and the second set is the PHY0 registers.
39 - description: Registers clock
40 - description: Main PHY clock
43 - description: Registers clock
44 - description: Main PHY clock
45 - description: ULPI PHY clock
48 - description: Registers clock
49 - description: Main PHY clock
50 - description: UTMI pads control registers clock
53 - description: Registers clock
54 - description: Main PHY clock
55 - description: UTMI timeout clock
56 - description: UTMI pads control registers clock
86 description: PHY reset
89 - description: PHY reset
90 - description: UTMI pads reset
104 $ref: /schemas/types.yaml#/definitions/string
105 enum: [utmi, ulpi, hsic]
108 $ref: /schemas/types.yaml#/definitions/string
109 enum: [host, peripheral, otg]
113 description: Regulator controlling USB VBUS.
115 nvidia,has-legacy-mode:
117 Indicates whether this controller can operate in legacy mode
118 (as APX 2500 / 2600). In legacy mode some registers are accessed
119 through the APB_MISC base address instead of the USB controller.
124 Indicates whether we can do certain kind of power optimizations for
125 the devices that are always connected. e.g. modem.
128 nvidia,has-utmi-pad-registers:
130 Indicates whether this controller contains the UTMI pad control
131 registers common to all USB controllers.
134 nvidia,hssync-start-delay:
135 $ref: /schemas/types.yaml#/definitions/uint32
139 Number of 480 MHz clock cycles to wait before start of sync launches
142 nvidia,elastic-limit:
143 $ref: /schemas/types.yaml#/definitions/uint32
146 description: Variable FIFO Depth of elastic input store.
148 nvidia,idle-wait-delay:
149 $ref: /schemas/types.yaml#/definitions/uint32
153 Number of 480 MHz clock cycles of idle to wait before declare IDLE.
155 nvidia,term-range-adj:
156 $ref: /schemas/types.yaml#/definitions/uint32
159 description: Range adjustment on terminations.
162 $ref: /schemas/types.yaml#/definitions/uint32
165 description: Input of XCVR cell, HS driver output control.
167 nvidia,xcvr-setup-use-fuses:
168 description: Indicates that the value is read from the on-chip fuses.
172 $ref: /schemas/types.yaml#/definitions/uint32
175 description: LS falling slew rate control.
178 $ref: /schemas/types.yaml#/definitions/uint32
181 description: LS rising slew rate control.
184 $ref: /schemas/types.yaml#/definitions/uint32
187 description: HS slew rate control.
189 nvidia,hssquelch-level:
190 $ref: /schemas/types.yaml#/definitions/uint32
193 description: HS squelch detector level.
195 nvidia,hsdiscon-level:
196 $ref: /schemas/types.yaml#/definitions/uint32
199 description: HS disconnect detector level.
201 nvidia,phy-reset-gpio:
203 description: GPIO used to reset the PHY.
206 $ref: /schemas/types.yaml#/definitions/phandle-array
209 - description: Phandle to Power Management controller.
210 - description: USB controller ID.
212 Phandle to Power Management controller.
224 additionalProperties: false
245 - nvidia,hssync-start-delay
246 - nvidia,elastic-limit
247 - nvidia,idle-wait-delay
248 - nvidia,term-range-adj
249 - nvidia,xcvr-lsfslew
250 - nvidia,xcvr-lsrslew
253 - required: ["nvidia,xcvr-setup"]
254 - required: ["nvidia,xcvr-setup-use-fuses"]
260 const: nvidia,tegra30-usb-phy
275 - nvidia,hssquelch-level
276 - nvidia,hsdiscon-level
329 #include <dt-bindings/clock/tegra124-car.h>
332 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
333 reg = <0x7d008000 0x4000>,
335 interrupts = <0 97 4>;
337 clocks = <&tegra_car TEGRA124_CLK_USB3>,
338 <&tegra_car TEGRA124_CLK_PLL_U>,
339 <&tegra_car TEGRA124_CLK_USBD>;
340 clock-names = "reg", "pll_u", "utmi-pads";
341 resets = <&tegra_car 59>, <&tegra_car 22>;
342 reset-names = "usb", "utmi-pads";
344 nvidia,hssync-start-delay = <0>;
345 nvidia,idle-wait-delay = <17>;
346 nvidia,elastic-limit = <16>;
347 nvidia,term-range-adj = <6>;
348 nvidia,xcvr-setup = <9>;
349 nvidia,xcvr-lsfslew = <0>;
350 nvidia,xcvr-lsrslew = <3>;
351 nvidia,hssquelch-level = <2>;
352 nvidia,hsdiscon-level = <5>;
353 nvidia,xcvr-hsslew = <12>;
354 nvidia,pmc = <&tegra_pmc 2>;
358 #include <dt-bindings/clock/tegra20-car.h>
361 compatible = "nvidia,tegra20-usb-phy";
362 reg = <0xc5004000 0x4000>;
363 interrupts = <0 21 4>;
365 clocks = <&tegra_car TEGRA20_CLK_USB2>,
366 <&tegra_car TEGRA20_CLK_PLL_U>,
367 <&tegra_car TEGRA20_CLK_CDEV2>;
368 clock-names = "reg", "pll_u", "ulpi-link";
369 resets = <&tegra_car 58>, <&tegra_car 22>;
370 reset-names = "usb", "utmi-pads";
372 nvidia,pmc = <&tegra_pmc 1>;