1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ========================================================
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5 signals) which connect directly to pins/pads on the SoC package. Each lane
6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
9 separately configured and powered up.
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
22 own subnode and can be referenced by users of the lane using the standard
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
25 The Tegra hardware documentation refers to the connection between the XUSB
26 pad controller and the XUSB controller as "ports". This is confusing since
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31 USB 3.0 receptacles, ...).
35 - compatible: Must be:
36 - Tegra124: "nvidia,tegra124-xusb-padctl"
37 - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38 - Tegra210: "nvidia,tegra210-xusb-padctl"
39 - Tegra186: "nvidia,tegra186-xusb-padctl"
40 - Tegra194: "nvidia,tegra194-xusb-padctl"
41 - reg: Physical base address and length of the controller's registers.
42 - resets: Must contain an entry for each entry in reset-names.
43 - reset-names: Must include the following entries:
47 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
48 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
49 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
50 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
53 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
54 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
55 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
56 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
57 - nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node.
60 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
61 power supply. Must supply 1.8 V.
62 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
64 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
65 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
68 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
70 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
75 A required child node named "pads" contains a list of subnodes, one for each
76 of the pads exposed by the XUSB pad controller. Each pad may need additional
77 resources that can be referenced in its pad node.
79 The "status" property is used to enable or disable the use of a pad. If set
80 to "disabled", the pad will not be used on the given board. In order to use
81 the pad and any of its lanes, this property must be set to "okay".
83 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
84 and sata. No extra resources are required for operation of these pads.
86 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
87 a description of the properties of each pad.
93 - clocks: Must contain an entry for each entry in clock-names.
94 - clock-names: Must contain the following entries:
95 - "trk": phandle and specifier referring to the USB2 tracking clock
101 - clocks: Must contain an entry for each entry in clock-names.
102 - clock-names: Must contain the following entries:
103 - "trk": phandle and specifier referring to the HSIC tracking clock
109 - clocks: Must contain an entry for each entry in clock-names.
110 - clock-names: Must contain the following entries:
111 - "pll": phandle and specifier referring to the PLLE
112 - resets: Must contain an entry for each entry in reset-names.
113 - reset-names: Must contain the following entries:
114 - "phy": reset for the PCIe UPHY block
120 - resets: Must contain an entry for each entry in reset-names.
121 - reset-names: Must contain the following entries:
122 - "phy": reset for the SATA UPHY block
128 Each pad node has a child named "lanes" that contains one or more children of
129 its own, each representing one of the lanes controlled by the pad.
133 - status: Defines the operation status of the PHY. Valid values are:
134 - "disabled": the PHY is disabled
135 - "okay": the PHY is enabled
136 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
137 no need for an additional specifier.
138 - nvidia,function: The output function of the PHY. See below for a list of
139 valid functions per SoC generation.
141 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
142 - usb2: usb2-0, usb2-1, usb2-2
143 - functions: "snps", "xusb", "uart"
145 - functions: "snps", "xusb"
146 - hsic: hsic-0, hsic-1
147 - functions: "snps", "xusb"
148 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
149 - functions: "pcie", "usb3-ss"
151 - functions: "usb3-ss", "sata"
153 For Tegra210, the list of valid PHY nodes is given below:
154 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
155 - functions: "snps", "xusb", "uart"
156 - hsic: hsic-0, hsic-1
157 - functions: "snps", "xusb"
158 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
159 - functions: "pcie-x1", "usb3-ss", "pcie-x4"
161 - functions: "usb3-ss", "sata"
163 For Tegra194, the list of valid PHY nodes is given below:
164 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
166 - usb3: usb3-0, usb3-1, usb3-2, usb3-3
172 A required child node named "ports" contains a list of all the ports exposed
173 by the XUSB pad controller. Per-port configuration is only required for USB.
179 - status: Defines the operation status of the port. Valid values are:
180 - "disabled": the port is disabled
181 - "okay": the port is enabled
182 - mode: A string that determines the mode in which to run the port. Valid
184 - "host": for USB host mode
185 - "device": for USB device mode
186 - "otg": for USB OTG mode
188 Required properties for OTG/Peripheral capable USB2 ports:
189 - usb-role-switch: Boolean property to indicate that the port support OTG or
190 peripheral mode. If present, the port supports switching between USB host
191 and peripheral roles. Connector should be added as subnode.
192 See usb/usb-conn-gpio.txt.
195 - nvidia,internal: A boolean property whose presence determines that a port
196 is internal. In the absence of this property the port is considered to be
198 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
204 - status: Defines the operation status of the port. Valid values are:
205 - "disabled": the port is disabled
206 - "okay": the port is enabled
207 - nvidia,internal: A boolean property whose presence determines that a port
208 is internal. In the absence of this property the port is considered to be
210 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
216 - status: Defines the operation status of the port. Valid values are:
217 - "disabled": the port is disabled
218 - "okay": the port is enabled
221 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
223 Super-speed USB ports:
224 ----------------------
227 - status: Defines the operation status of the port. Valid values are:
228 - "disabled": the port is disabled
229 - "okay": the port is enabled
230 - nvidia,usb2-companion: A single cell that specifies the physical port number
231 to map this super-speed USB port to. The range of valid port numbers varies
232 with the SoC generation:
233 - 0-2: for Tegra124 and Tegra132
237 - nvidia,internal: A boolean property whose presence determines that a port
238 is internal. In the absence of this property the port is considered to be
241 - maximum-speed: Only for Tegra194. A string property that specifies maximum
242 supported speed of a usb3 port. Valid values are:
243 - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
244 - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
246 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
248 - 3x USB2: usb2-0, usb2-1, usb2-2
250 - 2x HSIC: hsic-0, hsic-1
251 - 2x super-speed USB: usb3-0, usb3-1
253 For Tegra210, the XUSB pad controller exposes the following ports:
254 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
255 - 2x HSIC: hsic-0, hsic-1
256 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
258 For Tegra194, the XUSB pad controller exposes the following ports:
259 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
260 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
265 Tegra124 and Tegra132:
266 ----------------------
272 compatible = "nvidia,tegra124-xusb-padctl";
274 compatible = "nvidia,tegra132-xusb-padctl",
275 "nvidia,tegra124-xusb-padctl";
276 reg = <0x0 0x7009f000 0x0 0x1000>;
277 resets = <&tegra_car 142>;
278 reset-names = "padctl";
418 nvidia,function = "xusb";
423 nvidia,function = "xusb";
428 nvidia,function = "xusb";
439 nvidia,function = "usb3-ss";
444 nvidia,function = "pcie";
449 nvidia,function = "pcie";
460 nvidia,function = "sata";
485 vbus-supply = <&vdd_usb3_vbus>;
501 compatible = "nvidia,tegra210-xusb-padctl";
502 reg = <0x0 0x7009f000 0x0 0x1000>;
503 resets = <&tegra_car 142>;
504 reset-names = "padctl";
510 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
538 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
556 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
558 resets = <&tegra_car 205>;
601 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
603 resets = <&tegra_car 204>;
670 nvidia,function = "xusb";
675 nvidia,function = "xusb";
680 nvidia,function = "xusb";
685 nvidia,function = "xusb";
696 nvidia,function = "pcie-x1";
701 nvidia,function = "pcie-x4";
706 nvidia,function = "pcie-x4";
711 nvidia,function = "pcie-x4";
716 nvidia,function = "pcie-x4";
721 nvidia,function = "usb3-ss";
726 nvidia,function = "usb3-ss";
737 nvidia,function = "sata";
752 vbus-supply = <&vdd_5v0_rtl>;
758 vbus-supply = <&vdd_usb_vbus>;
769 nvidia,lanes = "pcie-6";
775 nvidia,lanes = "pcie-5";