1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ========================================================
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5 signals) which connect directly to pins/pads on the SoC package. Each lane
6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
9 separately configured and powered up.
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
22 own subnode and can be referenced by users of the lane using the standard
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
25 The Tegra hardware documentation refers to the connection between the XUSB
26 pad controller and the XUSB controller as "ports". This is confusing since
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31 USB 3.0 receptacles, ...).
35 - compatible: Must be:
36 - Tegra124: "nvidia,tegra124-xusb-padctl"
37 - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38 - Tegra210: "nvidia,tegra210-xusb-padctl"
39 - reg: Physical base address and length of the controller's registers.
40 - resets: Must contain an entry for each entry in reset-names.
41 - reset-names: Must include the following entries:
48 A required child node named "pads" contains a list of subnodes, one for each
49 of the pads exposed by the XUSB pad controller. Each pad may need additional
50 resources that can be referenced in its pad node.
52 The "status" property is used to enable or disable the use of a pad. If set
53 to "disabled", the pad will not be used on the given board. In order to use
54 the pad and any of its lanes, this property must be set to "okay".
56 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
57 and sata. No extra resources are required for operation of these pads.
59 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
60 a description of the properties of each pad.
66 - clocks: Must contain an entry for each entry in clock-names.
67 - clock-names: Must contain the following entries:
68 - "trk": phandle and specifier referring to the USB2 tracking clock
74 - clocks: Must contain an entry for each entry in clock-names.
75 - clock-names: Must contain the following entries:
76 - "trk": phandle and specifier referring to the HSIC tracking clock
82 - clocks: Must contain an entry for each entry in clock-names.
83 - clock-names: Must contain the following entries:
84 - "pll": phandle and specifier referring to the PLLE
85 - resets: Must contain an entry for each entry in reset-names.
86 - reset-names: Must contain the following entries:
87 - "phy": reset for the PCIe UPHY block
93 - resets: Must contain an entry for each entry in reset-names.
94 - reset-names: Must contain the following entries:
95 - "phy": reset for the SATA UPHY block
101 Each pad node has a child named "lanes" that contains one or more children of
102 its own, each representing one of the lanes controlled by the pad.
106 - status: Defines the operation status of the PHY. Valid values are:
107 - "disabled": the PHY is disabled
108 - "okay": the PHY is enabled
109 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
110 no need for an additional specifier.
111 - nvidia,function: The output function of the PHY. See below for a list of
112 valid functions per SoC generation.
114 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
115 - usb2: usb2-0, usb2-1, usb2-2
116 - functions: "snps", "xusb", "uart"
118 - functions: "snps", "xusb"
119 - hsic: hsic-0, hsic-1
120 - functions: "snps", "xusb"
121 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
122 - functions: "pcie", "usb3-ss"
124 - functions: "usb3-ss", "sata"
126 For Tegra210, the list of valid PHY nodes is given below:
127 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
128 - functions: "snps", "xusb", "uart"
129 - hsic: hsic-0, hsic-1
130 - functions: "snps", "xusb"
131 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
132 - functions: "pcie-x1", "usb3-ss", "pcie-x4"
134 - functions: "usb3-ss", "sata"
140 A required child node named "ports" contains a list of all the ports exposed
141 by the XUSB pad controller. Per-port configuration is only required for USB.
147 - status: Defines the operation status of the port. Valid values are:
148 - "disabled": the port is disabled
149 - "okay": the port is enabled
150 - mode: A string that determines the mode in which to run the port. Valid
152 - "host": for USB host mode
153 - "device": for USB device mode
154 - "otg": for USB OTG mode
157 - nvidia,internal: A boolean property whose presence determines that a port
158 is internal. In the absence of this property the port is considered to be
160 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
166 - status: Defines the operation status of the port. Valid values are:
167 - "disabled": the port is disabled
168 - "okay": the port is enabled
169 - nvidia,internal: A boolean property whose presence determines that a port
170 is internal. In the absence of this property the port is considered to be
172 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
178 - status: Defines the operation status of the port. Valid values are:
179 - "disabled": the port is disabled
180 - "okay": the port is enabled
183 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
185 Super-speed USB ports:
186 ----------------------
189 - status: Defines the operation status of the port. Valid values are:
190 - "disabled": the port is disabled
191 - "okay": the port is enabled
192 - nvidia,usb2-companion: A single cell that specifies the physical port number
193 to map this super-speed USB port to. The range of valid port numbers varies
194 with the SoC generation:
195 - 0-2: for Tegra124 and Tegra132
199 - nvidia,internal: A boolean property whose presence determines that a port
200 is internal. In the absence of this property the port is considered to be
203 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
205 - 3x USB2: usb2-0, usb2-1, usb2-2
207 - 2x HSIC: hsic-0, hsic-1
208 - 2x super-speed USB: usb3-0, usb3-1
210 For Tegra210, the XUSB pad controller exposes the following ports:
211 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
212 - 2x HSIC: hsic-0, hsic-1
213 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
219 Tegra124 and Tegra132:
220 ----------------------
226 compatible = "nvidia,tegra124-xusb-padctl";
228 compatible = "nvidia,tegra132-xusb-padctl",
229 "nvidia,tegra124-xusb-padctl";
230 reg = <0x0 0x7009f000 0x0 0x1000>;
231 resets = <&tegra_car 142>;
232 reset-names = "padctl";
372 nvidia,function = "xusb";
377 nvidia,function = "xusb";
382 nvidia,function = "xusb";
393 nvidia,function = "usb3-ss";
398 nvidia,function = "pcie";
403 nvidia,function = "pcie";
414 nvidia,function = "sata";
439 vbus-supply = <&vdd_usb3_vbus>;
455 compatible = "nvidia,tegra210-xusb-padctl";
456 reg = <0x0 0x7009f000 0x0 0x1000>;
457 resets = <&tegra_car 142>;
458 reset-names = "padctl";
464 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
492 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
510 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
512 resets = <&tegra_car 205>;
555 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
557 resets = <&tegra_car 204>;
624 nvidia,function = "xusb";
629 nvidia,function = "xusb";
634 nvidia,function = "xusb";
639 nvidia,function = "xusb";
650 nvidia,function = "pcie-x1";
655 nvidia,function = "pcie-x4";
660 nvidia,function = "pcie-x4";
665 nvidia,function = "pcie-x4";
670 nvidia,function = "pcie-x4";
675 nvidia,function = "usb3-ss";
680 nvidia,function = "usb3-ss";
691 nvidia,function = "sata";
706 vbus-supply = <&vdd_5v0_rtl>;
712 vbus-supply = <&vdd_usb_vbus>;
723 nvidia,lanes = "pcie-6";
729 nvidia,lanes = "pcie-5";