Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mixel DSI PHY for i.MX8
   8
   9 maintainers:
  10   - Guido Günther <agx@sigxcpu.org>
  11
  12 description: |
  13   The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
  14   MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
  15   electrical signals for DSI.
  16
  17   The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
  18   in either MIPI-DSI PHY mode or LVDS PHY mode.
  19
  20 properties:
  21   compatible:
  22     enum:
  23       - fsl,imx8mq-mipi-dphy
  24       - fsl,imx8qxp-mipi-dphy
  25
  26   reg:
  27     maxItems: 1
  28
  29   clocks:
  30     maxItems: 1
  31
  32   clock-names:
  33     const: phy_ref
  34
  35   assigned-clocks:
  36     maxItems: 1
  37
  38   assigned-clock-parents:
  39     maxItems: 1
  40
  41   assigned-clock-rates:
  42     maxItems: 1
  43
  44   "#phy-cells":
  45     const: 0
  46
  47   fsl,syscon:
  48     $ref: /schemas/types.yaml#/definitions/phandle
  49     description: |
  50       A phandle which points to Control and Status Registers(CSR) module.
  51
  52   power-domains:
  53     maxItems: 1
  54
  55 required:
  56   - compatible
  57   - reg
  58   - clocks
  59   - clock-names
  60   - "#phy-cells"
  61   - power-domains
  62
  63 allOf:
  64   - if:
  65       properties:
  66         compatible:
  67           contains:
  68             const: fsl,imx8mq-mipi-dphy
  69     then:
  70       properties:
  71         fsl,syscon: false
  72
  73       required:
  74         - assigned-clocks
  75         - assigned-clock-parents
  76         - assigned-clock-rates
  77
  78   - if:
  79       properties:
  80         compatible:
  81           contains:
  82             const: fsl,imx8qxp-mipi-dphy
  83     then:
  84       properties:
  85         assigned-clocks: false
  86         assigned-clock-parents: false
  87         assigned-clock-rates: false
  88
  89       required:
  90         - fsl,syscon
  91
  92 additionalProperties: false
  93
  94 examples:
  95   - |
  96     #include <dt-bindings/clock/imx8mq-clock.h>
  97     dphy: dphy@30a0030 {
  98         compatible = "fsl,imx8mq-mipi-dphy";
  99         reg = <0x30a00300 0x100>;
 100         clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 101         clock-names = "phy_ref";
 102         assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 103         assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 104         assigned-clock-rates = <24000000>;
 105         #phy-cells = <0>;
 106         power-domains = <&pgc_mipi>;
 107     };