Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale i.MX8 SoC series PCIe PHY
   8
   9 maintainers:
  10   - Richard Zhu <hongxing.zhu@nxp.com>
  11
  12 properties:
  13   "#phy-cells":
  14     const: 0
  15
  16   compatible:
  17     enum:
  18       - fsl,imx8mm-pcie-phy
  19       - fsl,imx8mp-pcie-phy
  20
  21   reg:
  22     maxItems: 1
  23
  24   clocks:
  25     maxItems: 1
  26
  27   clock-names:
  28     items:
  29       - const: ref
  30
  31   resets:
  32     minItems: 1
  33     maxItems: 2
  34
  35   reset-names:
  36     oneOf:
  37       - items:          # for iMX8MM
  38           - const: pciephy
  39       - items:          # for IMX8MP
  40           - const: pciephy
  41           - const: perst
  42
  43   fsl,refclk-pad-mode:
  44     description: |
  45       Specifies the mode of the refclk pad used. It can be UNUSED(PHY
  46       refclock is derived from SoC internal source), INPUT(PHY refclock
  47       is provided externally via the refclk pad) or OUTPUT(PHY refclock
  48       is derived from SoC internal source and provided on the refclk pad).
  49       Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
  50       to be used.
  51     $ref: /schemas/types.yaml#/definitions/uint32
  52     enum: [ 0, 1, 2 ]
  53
  54   fsl,tx-deemph-gen1:
  55     description: Gen1 De-emphasis value (optional).
  56     $ref: /schemas/types.yaml#/definitions/uint32
  57     default: 0
  58
  59   fsl,tx-deemph-gen2:
  60     description: Gen2 De-emphasis value (optional).
  61     $ref: /schemas/types.yaml#/definitions/uint32
  62     default: 0
  63
  64   fsl,clkreq-unsupported:
  65     type: boolean
  66     description: A boolean property indicating the CLKREQ# signal is
  67       not supported in the board design (optional)
  68
  69   power-domains:
  70     description: PCIe PHY  power domain (optional).
  71     maxItems: 1
  72
  73 required:
  74   - "#phy-cells"
  75   - compatible
  76   - reg
  77   - clocks
  78   - clock-names
  79   - fsl,refclk-pad-mode
  80
  81 additionalProperties: false
  82
  83 examples:
  84   - |
  85     #include <dt-bindings/clock/imx8mm-clock.h>
  86     #include <dt-bindings/phy/phy-imx8-pcie.h>
  87     #include <dt-bindings/reset/imx8mq-reset.h>
  88
  89     pcie_phy: pcie-phy@32f00000 {
  90             compatible = "fsl,imx8mm-pcie-phy";
  91             reg = <0x32f00000 0x10000>;
  92             clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
  93             clock-names = "ref";
  94             assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
  95             assigned-clock-rates = <100000000>;
  96             assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
  97             resets = <&src IMX8MQ_RESET_PCIEPHY>;
  98             reset-names = "pciephy";
  99             fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 100             #phy-cells = <0>;
 101     };
 102 ...