1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H3 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
24 - description: PHY Control registers
25 - description: PHY PMU0 registers
26 - description: PHY PMU1 registers
27 - description: PHY PMU2 registers
28 - description: PHY PMU3 registers
40 - description: USB OTG PHY bus clock
41 - description: USB Host 0 PHY bus clock
42 - description: USB Host 1 PHY bus clock
43 - description: USB Host 2 PHY bus clock
54 - description: USB OTG reset
55 - description: USB Host 1 Controller reset
56 - description: USB Host 2 Controller reset
57 - description: USB Host 3 Controller reset
68 description: GPIO to the USB OTG ID pin
72 description: GPIO to the USB OTG VBUS detect pin
74 usb0_vbus_power-supply:
75 description: Power supply to detect the USB OTG VBUS
78 description: Regulator controlling USB OTG VBUS
81 description: Regulator controlling USB1 Host controller
84 description: Regulator controlling USB2 Host controller
87 description: Regulator controlling USB3 Host controller
99 additionalProperties: false
103 #include <dt-bindings/gpio/gpio.h>
104 #include <dt-bindings/clock/sun8i-h3-ccu.h>
105 #include <dt-bindings/reset/sun8i-h3-ccu.h>
109 compatible = "allwinner,sun8i-h3-usb-phy";
110 reg = <0x01c19400 0x2c>,
115 reg-names = "phy_ctrl",
120 clocks = <&ccu CLK_USB_PHY0>,
124 clock-names = "usb0_phy",
128 resets = <&ccu RST_USB_PHY0>,
132 reset-names = "usb0_reset",
136 usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
137 usb0_vbus-supply = <®_usb0_vbus>;
138 usb1_vbus-supply = <®_usb1_vbus>;
139 usb2_vbus-supply = <®_usb2_vbus>;
140 usb3_vbus-supply = <®_usb3_vbus>;