1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm SMMUv3 Performance Monitor Counter Group
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <robin.murphy@arm.com>
14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
15 They are standalone performance monitoring units that support both
16 architected and IMPLEMENTATION DEFINED event counters.
20 pattern: "^pmu@[0-9a-f]*"
24 - const: arm,mmu-600-pmcg
25 - const: arm,smmu-v3-pmcg
26 - const: arm,smmu-v3-pmcg
30 - description: Register page 0
31 - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
49 additionalProperties: false
53 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/interrupt-controller/irq.h>
57 compatible = "arm,smmu-v3-pmcg";
58 reg = <0x2b420000 0x1000>,
60 interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
61 msi-parent = <&its 0xff0000>;
65 compatible = "arm,smmu-v3-pmcg";
66 reg = <0x2b440000 0x1000>,
68 interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
69 msi-parent = <&its 0xff0000>;