1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx XDMA PL PCIe Root Port Bridge
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,xdma-host-3.00
27 - description: interrupt asserted when miscellaneous interrupt is received.
28 - description: msi0 interrupt asserted when an MSI is received.
29 - description: msi1 interrupt asserted when an MSI is received.
51 description: identifies the node as an interrupt controller
54 interrupt-controller: true
63 - interrupt-controller
67 additionalProperties: false
77 - interrupt-controller
79 unevaluatedProperties: false
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 #include <dt-bindings/interrupt-controller/irq.h>
91 compatible = "xlnx,xdma-host-3.00";
92 reg = <0x0 0xa0000000 0x0 0x10000000>;
93 ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
94 <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
97 #interrupt-cells = <1>;
99 interrupt-parent = <&gic>;
100 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "misc", "msi0", "msi1";
103 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
104 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
105 <0 0 0 2 &pcie_intc_0 1>,
106 <0 0 0 3 &pcie_intc_0 2>,
107 <0 0 0 4 &pcie_intc_0 3>;
108 pcie_intc_0: interrupt-controller {
109 #address-cells = <0>;
110 #interrupt-cells = <1>;
111 interrupt-controller;