1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI PCIe Root Port Bridge
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,axi-pcie-host-1.00.a
28 ranges for the PCI memory regions (I/O space region is not
29 supported by hardware)
35 description: identifies the node as an interrupt controller
38 interrupt-controller: true
47 - interrupt-controller
51 additionalProperties: false
60 - interrupt-controller
62 unevaluatedProperties: false
66 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 #include <dt-bindings/interrupt-controller/irq.h>
70 compatible = "xlnx,axi-pcie-host-1.00.a";
71 reg = <0x50000000 0x1000000>;
74 #interrupt-cells = <1>;
76 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-map-mask = <0 0 0 7>;
78 interrupt-map = <0 0 0 1 &pcie_intc 1>,
79 <0 0 0 2 &pcie_intc 2>,
80 <0 0 0 3 &pcie_intc 3>,
81 <0 0 0 4 &pcie_intc 4>;
82 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>;
83 pcie_intc: interrupt-controller {
86 #interrupt-cells = <1>;