Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: CPM Host Controller device tree for Xilinx Versal SoCs
   8
   9 maintainers:
  10   - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
  11
  12 allOf:
  13   - $ref: /schemas/pci/pci-bus.yaml#
  14
  15 properties:
  16   compatible:
  17     enum:
  18       - xlnx,versal-cpm-host-1.00
  19       - xlnx,versal-cpm5-host
  20
  21   reg:
  22     items:
  23       - description: CPM system level control and status registers.
  24       - description: Configuration space region and bridge registers.
  25       - description: CPM5 control and status registers.
  26     minItems: 2
  27
  28   reg-names:
  29     items:
  30       - const: cpm_slcr
  31       - const: cfg
  32       - const: cpm_csr
  33     minItems: 2
  34
  35   interrupts:
  36     maxItems: 1
  37
  38   msi-map:
  39     description:
  40       Maps a Requester ID to an MSI controller and associated MSI sideband data.
  41
  42   ranges:
  43     maxItems: 2
  44
  45   "#interrupt-cells":
  46     const: 1
  47
  48   interrupt-controller:
  49     description: Interrupt controller node for handling legacy PCI interrupts.
  50     type: object
  51     properties:
  52       "#address-cells":
  53         const: 0
  54       "#interrupt-cells":
  55         const: 1
  56       "interrupt-controller": true
  57     additionalProperties: false
  58
  59 required:
  60   - reg
  61   - reg-names
  62   - "#interrupt-cells"
  63   - interrupts
  64   - interrupt-map
  65   - interrupt-map-mask
  66   - bus-range
  67   - msi-map
  68   - interrupt-controller
  69
  70 unevaluatedProperties: false
  71
  72 examples:
  73   - |
  74
  75     versal {
  76                #address-cells = <2>;
  77                #size-cells = <2>;
  78                cpm_pcie: pcie@fca10000 {
  79                        compatible = "xlnx,versal-cpm-host-1.00";
  80                        device_type = "pci";
  81                        #address-cells = <3>;
  82                        #interrupt-cells = <1>;
  83                        #size-cells = <2>;
  84                        interrupts = <0 72 4>;
  85                        interrupt-parent = <&gic>;
  86                        interrupt-map-mask = <0 0 0 7>;
  87                        interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
  88                                        <0 0 0 2 &pcie_intc_0 1>,
  89                                        <0 0 0 3 &pcie_intc_0 2>,
  90                                        <0 0 0 4 &pcie_intc_0 3>;
  91                        bus-range = <0x00 0xff>;
  92                        ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
  93                                 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
  94                        msi-map = <0x0 &its_gic 0x0 0x10000>;
  95                        reg = <0x0 0xfca10000 0x0 0x1000>,
  96                              <0x6 0x00000000 0x0 0x10000000>;
  97                        reg-names = "cpm_slcr", "cfg";
  98                        pcie_intc_0: interrupt-controller {
  99                                #address-cells = <0>;
 100                                #interrupt-cells = <1>;
 101                                interrupt-controller;
 102                        };
 103                };
 104
 105                cpm5_pcie: pcie@fcdd0000 {
 106                        compatible = "xlnx,versal-cpm5-host";
 107                        device_type = "pci";
 108                        #address-cells = <3>;
 109                        #interrupt-cells = <1>;
 110                        #size-cells = <2>;
 111                        interrupts = <0 72 4>;
 112                        interrupt-parent = <&gic>;
 113                        interrupt-map-mask = <0 0 0 7>;
 114                        interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
 115                                        <0 0 0 2 &pcie_intc_1 1>,
 116                                        <0 0 0 3 &pcie_intc_1 2>,
 117                                        <0 0 0 4 &pcie_intc_1 3>;
 118                        bus-range = <0x00 0xff>;
 119                        ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
 120                                 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
 121                        msi-map = <0x0 &its_gic 0x0 0x10000>;
 122                        reg = <0x00 0xfcdd0000 0x00 0x1000>,
 123                              <0x06 0x00000000 0x00 0x1000000>,
 124                              <0x00 0xfce20000 0x00 0x1000000>;
 125                        reg-names = "cpm_slcr", "cfg", "cpm_csr";
 126
 127                        pcie_intc_1: interrupt-controller {
 128                                #address-cells = <0>;
 129                                #interrupt-cells = <1>;
 130                                interrupt-controller;
 131                        };
 132                };
 133
 134     };