1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
32 description: Phandle to the SYSCON entry required for configuring PCIe mode
34 $ref: /schemas/types.yaml#/definitions/phandle
41 description: clock-specifier to represent input to the PCIe
75 unevaluatedProperties: false
79 #include <dt-bindings/soc/ti,sci_pm_domain.h>
80 #include <dt-bindings/gpio/gpio.h>
86 pcie0_rc: pcie@2900000 {
87 compatible = "ti,j721e-pcie-host";
88 reg = <0x00 0x02900000 0x00 0x1000>,
89 <0x00 0x02907000 0x00 0x400>,
90 <0x00 0x0d000000 0x00 0x00800000>,
91 <0x00 0x10000000 0x00 0x00001000>;
92 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
93 ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
96 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
97 clocks = <&k3_clks 239 1>;
100 #address-cells = <3>;
102 bus-range = <0x0 0xf>;
103 vendor-id = <0x104c>;
104 device-id = <0xb00d>;
105 msi-map = <0x0 &gic_its 0x0 0x10000>;
107 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
108 phys = <&serdes0_pcie_link>;
109 phy-names = "pcie-phy";
110 ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
111 <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
112 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;