1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
26 - $ref: /schemas/pci/pci-bus.yaml#
27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
41 At least DBI reg-space and peripheral devices CFG-space outbound window
42 are required for the normal controller work. iATU memory IO region is
43 also required if the space is unrolled (IP-core version >= 4.80a).
53 Basic DWC PCIe controller configuration-space accessible over
54 the DBI interface. This memory space is either activated with
55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
57 via the PL viewports on the DWC PCIe controllers older than
61 Shadow DWC PCIe config-space registers. This space is selected
62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
63 the PCI-SIG PCIe CFG-space with the shadow registers for some
64 PCI Header space, PCI Standard and Extended Structures. It's
65 mainly relevant for the end-point controller configuration,
66 but still there are some shadow registers available for the
70 External Local Bus registers. It's an application-dependent
71 registers normally defined by the platform engineers. The space
72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
73 be accessed over some platform-specific means (for instance
74 as a part of a system controller).
77 iATU/eDMA registers common for all device functions. It's an
78 unrolled memory space with the internal Address Translation
79 Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
80 and CS2 = 1. For IP-core releases prior v4.80a, these registers
81 have been programmed via an indirect addressing scheme using a
82 set of viewport CSRs mapped into the PL space. Note iATU is
83 normally mapped to the 0x0 address of this region, while eDMA
84 is available at 0x80000 base address.
87 Platform-specific eDMA registers. Some platforms may have eDMA
88 CSRs mapped in a non-standard base address. The registers offset
89 can be changed or the MS/LS-bits of the address can be attached
90 in an additional RTL block before the MEM-IO transactions reach
91 the DW PCIe slave interface.
94 PHY/PCS configuration registers. Some platforms can have the
95 PCS and PHY CSRs accessible over a dedicated memory mapped
96 region, but mainly these registers are indirectly accessible
97 either by means of the embedded PHY viewport schema or by some
98 platform-specific method.
101 Outbound iATU-capable memory-region which will be used to access
102 the peripheral PCIe devices configuration space.
105 Vendor-specific CSR names. Consider using the generic names above
108 - description: See native 'elbi/app' CSR region for details.
109 enum: [ apb, mgmt, link, ulreg, appl ]
110 - description: See native 'atu' CSR region for details.
112 - description: Syscon-related CSR regions.
114 - description: Tegra234 aperture
124 DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
125 signal is supposed to be specified for the host controller.
135 Controller request to read or write virtual product data
136 from/to the VPD capability registers.
139 Link Equalization Request flag is set in the Link Status 2
140 register (applicable if the corresponding IRQ is enabled in
141 the Link Control 3 register).
144 Indicates that the eDMA Tx/Rx transfer is complete or that an
145 error has occurred on the corresponding channel. eDMA can have
146 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
147 to 16 IRQ signals all together. Write eDMA channels shall go
148 first in the ordered row as per default edma_int[*] bus setup.
149 pattern: '^dma([0-9]|1[0-5])?$'
151 PCIe protocol correctable error or a Data Path protection
152 correctable error is detected by the automotive/safety
156 Indicates that the internal safety mechanism has detected an
160 Application-specific IRQ raised depending on the vendor-specific
164 DSP AXI MSI Interrupt detected. It gets de-asserted when there is
165 no more MSI interrupt pending. The interrupt is relevant to the
166 iMSI-RX - Integrated MSI Receiver (AXI bridge).
169 Legacy A/B/C/D interrupt signal. Basically it's triggered by
170 receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message
171 from the downstream device.
172 pattern: "^int(a|b|c|d)$"
174 Error condition detected and a flag is set in the Root Error Status
175 register of the AER capability. It's asserted when the RC
176 internally generated an error or an error message is received by
180 PME message is received by the port. That means having the PME
181 status bit set in the Root Status register (the event is
182 supposed to be unmasked in the Root Control register).
185 Hot-plug event is detected. That is a bit has been set in the
186 Slot Status register and the corresponding event is enabled in
187 the Slot Control register.
190 Link Autonomous Bandwidth Status flag has been set in the Link
191 Status register (the event is supposed to be unmasked in the
192 Link Control register).
195 Bandwidth Management Status flag has been set in the Link
196 Status register (the event is supposed to be unmasked in the
197 Link Control register).
200 Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for
204 Vendor-specific IRQ names. Consider using the generic names above
207 - description: See native "app" IRQ for details
208 enum: [ intr, sys, pmc, msg, err ]
210 additionalProperties: true
220 compatible = "snps,dw-pcie";
222 reg = <0xdfc00000 0x0001000>, /* IP registers */
223 <0xd0000000 0x0002000>; /* Configuration space */
224 reg-names = "dbi", "config";
225 #address-cells = <3>;
227 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
228 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
229 bus-range = <0x0 0xff>;
231 interrupts = <25>, <24>;
232 interrupt-names = "msi", "hp";
233 #interrupt-cells = <1>;
235 reset-gpios = <&port0 0 1>;
241 max-link-speed = <3>;