GNU Linux-libre 4.14.266-gnu1
[releases.git] / Documentation / devicetree / bindings / pci / samsung,exynos5440-pcie.txt
1 * Samsung Exynos 5440 PCIe interface
2
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
5
6 Required properties:
7 - compatible: "samsung,exynos5440-pcie"
8 - reg: base addresses and lengths of the PCIe controller,
9         the PHY controller, additional register for the PHY controller.
10         (Registers for the PHY controller are DEPRECATED.
11          Use the PHY framework.)
12 - reg-names : First name should be set to "elbi".
13         And use the "config" instead of getting the configuration address space
14         from "ranges".
15         NOTE: When using the "config" property, reg-names must be set.
16 - interrupts: A list of interrupt outputs for level interrupt,
17         pulse interrupt, special interrupt.
18 - phys: From PHY binding. Phandle for the generic PHY.
19         Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
20
21 For other common properties, refer to
22         Documentation/devicetree/bindings/pci/designware-pcie.txt
23
24 Example:
25
26 SoC-specific DT Entry:
27
28         pcie@290000 {
29                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
30                 reg = <0x290000 0x1000
31                         0x270000 0x1000
32                         0x271000 0x40>;
33                 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
34                 clocks = <&clock 28>, <&clock 27>;
35                 clock-names = "pcie", "pcie_bus";
36                 #address-cells = <3>;
37                 #size-cells = <2>;
38                 device_type = "pci";
39                 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
40                           0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
41                           0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
42                 #interrupt-cells = <1>;
43                 interrupt-map-mask = <0 0 0 0>;
44                 interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
45                 num-lanes = <4>;
46         };
47
48         pcie@2a0000 {
49                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
50                 reg = <0x2a0000 0x1000
51                         0x272000 0x1000
52                         0x271040 0x40>;
53                 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
54                 clocks = <&clock 29>, <&clock 27>;
55                 clock-names = "pcie", "pcie_bus";
56                 #address-cells = <3>;
57                 #size-cells = <2>;
58                 device_type = "pci";
59                 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
60                           0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
61                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
62                 #interrupt-cells = <1>;
63                 interrupt-map-mask = <0 0 0 0>;
64                 interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
65                 num-lanes = <4>;
66         };
67
68 With using PHY framework:
69         pcie_phy0: pcie-phy@270000 {
70                 ...
71                 reg = <0x270000 0x1000>, <0x271000 0x40>;
72                 reg-names = "phy", "block";
73                 ...
74         };
75
76         pcie@290000 {
77                 ...
78                 reg = <0x290000 0x1000>, <0x40000000 0x1000>;
79                 reg-names = "elbi", "config";
80                 phys = <&pcie_phy0>;
81                 ranges = <0x81000000 0 0          0x60001000 0 0x00010000
82                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
83                 ...
84         };
85
86 Board-specific DT Entry:
87
88         pcie@290000 {
89                 reset-gpio = <&pin_ctrl 5 0>;
90         };
91
92         pcie@2a0000 {
93                 reset-gpio = <&pin_ctrl 22 0>;
94         };