1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common properties defined in
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
25 - const: rockchip,rk3568-pcie
28 - rockchip,rk3588-pcie
29 - const: rockchip,rk3568-pcie
33 - description: Data Bus Interface (DBI) registers
34 - description: Rockchip designed configuration registers
35 - description: Config registers
46 - description: AHB clock for PCIe master
47 - description: AHB clock for PCIe slave
48 - description: AHB clock for PCIe dbi
49 - description: APB clock for PCIe
50 - description: Auxiliary clock for PCIe
51 - description: PIPE clock
66 Combined system interrupt, which is used to signal the following
67 interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
68 hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
69 edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
71 Combined PM interrupt, which is used to signal the following
72 interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
73 linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
74 linkst_out_l0s, pm_dstate_update
76 Combined message interrupt, which is used to signal the following
77 interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
78 pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
80 Combined legacy interrupt, which is used to signal the following
81 interrupts - inta, intb, intc, intd
83 Combined error interrupt, which is used to signal the following
84 interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
85 tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
86 nf_err_rx, f_err_rx, radm_qoverflow
96 legacy-interrupt-controller:
97 description: Interrupt controller node for handling legacy PCI interrupts.
99 additionalProperties: false
107 interrupt-controller: true
111 - description: combined legacy interrupt
115 - interrupt-controller
146 vpcie3v3-supply: true
162 unevaluatedProperties: false
166 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 #address-cells = <2>;
172 pcie3x2: pcie@fe280000 {
173 compatible = "rockchip,rk3568-pcie";
174 reg = <0x3 0xc0800000 0x0 0x390000>,
175 <0x0 0xfe280000 0x0 0x10000>,
176 <0x3 0x80000000 0x0 0x100000>;
177 reg-names = "dbi", "apb", "config";
178 bus-range = <0x20 0x2f>;
179 clocks = <&cru 143>, <&cru 144>,
180 <&cru 145>, <&cru 146>,
182 clock-names = "aclk_mst", "aclk_slv",
186 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
192 linux,pci-domain = <2>;
193 max-link-speed = <2>;
194 msi-map = <0x2000 &its 0x2000 0x1000>;
197 phy-names = "pcie-phy";
198 power-domains = <&power 15>;
199 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
200 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
202 reset-names = "pipe";
203 #address-cells = <3>;
206 legacy-interrupt-controller {
207 interrupt-controller;
208 #address-cells = <0>;
209 #interrupt-cells = <1>;
210 interrupt-parent = <&gic>;
211 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;