Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Renesas R-Car PCIe Endpoint
   9
  10 maintainers:
  11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  12   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  13
  14 properties:
  15   compatible:
  16     items:
  17       - enum:
  18           - renesas,r8a774a1-pcie-ep     # RZ/G2M
  19           - renesas,r8a774b1-pcie-ep     # RZ/G2N
  20           - renesas,r8a774c0-pcie-ep     # RZ/G2E
  21           - renesas,r8a774e1-pcie-ep     # RZ/G2H
  22           - renesas,r8a7795-pcie-ep      # R-Car H3
  23       - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
  24
  25   reg:
  26     maxItems: 5
  27
  28   reg-names:
  29     items:
  30       - const: apb-base
  31       - const: memory0
  32       - const: memory1
  33       - const: memory2
  34       - const: memory3
  35
  36   interrupts:
  37     minItems: 3
  38     maxItems: 3
  39
  40   power-domains:
  41     maxItems: 1
  42
  43   resets:
  44     maxItems: 1
  45
  46   clocks:
  47     maxItems: 1
  48
  49   clock-names:
  50     items:
  51       - const: pcie
  52
  53   max-functions:
  54     minimum: 1
  55     maximum: 1
  56
  57 required:
  58   - compatible
  59   - reg
  60   - reg-names
  61   - interrupts
  62   - resets
  63   - power-domains
  64   - clocks
  65   - clock-names
  66   - max-functions
  67
  68 additionalProperties: false
  69
  70 examples:
  71   - |
  72     #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
  73     #include <dt-bindings/interrupt-controller/arm-gic.h>
  74     #include <dt-bindings/power/r8a774c0-sysc.h>
  75
  76      pcie0_ep: pcie-ep@fe000000 {
  77             compatible = "renesas,r8a774c0-pcie-ep",
  78                          "renesas,rcar-gen3-pcie-ep";
  79             reg = <0xfe000000 0x80000>,
  80                   <0xfe100000 0x100000>,
  81                   <0xfe200000 0x200000>,
  82                   <0x30000000 0x8000000>,
  83                   <0x38000000 0x8000000>;
  84             reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
  85             interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  86                          <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  87                          <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  88             resets = <&cpg 319>;
  89             power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
  90             clocks = <&cpg CPG_MOD 319>;
  91             clock-names = "pcie";
  92             max-functions = /bits/ 8 <1>;
  93     };