Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Renesas R-Car Gen4 PCIe Host
   9
  10 maintainers:
  11   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  12
  13 allOf:
  14   - $ref: snps,dw-pcie.yaml#
  15
  16 properties:
  17   compatible:
  18     items:
  19       - const: renesas,r8a779f0-pcie   # R-Car S4-8
  20       - const: renesas,rcar-gen4-pcie  # R-Car Gen4
  21
  22   reg:
  23     maxItems: 7
  24
  25   reg-names:
  26     items:
  27       - const: dbi
  28       - const: dbi2
  29       - const: atu
  30       - const: dma
  31       - const: app
  32       - const: phy
  33       - const: config
  34
  35   interrupts:
  36     maxItems: 4
  37
  38   interrupt-names:
  39     items:
  40       - const: msi
  41       - const: dma
  42       - const: sft_ce
  43       - const: app
  44
  45   clocks:
  46     maxItems: 2
  47
  48   clock-names:
  49     items:
  50       - const: core
  51       - const: ref
  52
  53   power-domains:
  54     maxItems: 1
  55
  56   resets:
  57     maxItems: 1
  58
  59   reset-names:
  60     items:
  61       - const: pwr
  62
  63   max-link-speed:
  64     maximum: 4
  65
  66   num-lanes:
  67     maximum: 4
  68
  69 required:
  70   - compatible
  71   - reg
  72   - reg-names
  73   - interrupts
  74   - interrupt-names
  75   - clocks
  76   - clock-names
  77   - power-domains
  78   - resets
  79   - reset-names
  80
  81 unevaluatedProperties: false
  82
  83 examples:
  84   - |
  85     #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
  86     #include <dt-bindings/interrupt-controller/arm-gic.h>
  87     #include <dt-bindings/power/r8a779f0-sysc.h>
  88
  89     soc {
  90         #address-cells = <2>;
  91         #size-cells = <2>;
  92
  93         pcie: pcie@e65d0000 {
  94             compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
  95             reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
  96                   <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
  97                   <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
  98                   <0 0xfe000000 0 0x400000>;
  99             reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
 100             interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 101                          <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 102                          <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 103                          <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 104             interrupt-names = "msi", "dma", "sft_ce", "app";
 105             clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 106             clock-names = "core", "ref";
 107             power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 108             resets = <&cpg 624>;
 109             reset-names = "pwr";
 110             max-link-speed = <4>;
 111             num-lanes = <2>;
 112             #address-cells = <3>;
 113             #size-cells = <2>;
 114             bus-range = <0x00 0xff>;
 115             device_type = "pci";
 116             ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
 117                      <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
 118             dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
 119             #interrupt-cells = <1>;
 120             interrupt-map-mask = <0 0 0 7>;
 121             interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 122                             <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 123                             <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 124                             <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
 125             snps,enable-cdm-check;
 126         };
 127     };