1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCI express root complex
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
26 - qcom,pcie-ipq8064-v2
28 - qcom,pcie-ipq8074-gen3
41 - qcom,pcie-sm8450-pcie0
42 - qcom,pcie-sm8450-pcie1
47 - const: qcom,pcie-sm8550
49 - const: qcom,pcie-msm8998
50 - const: qcom,pcie-msm8996
72 # Common definitions for clocks, clock-names and reset.
73 # Platform constraints are described later.
101 description: A phandle to the core analog power supply
104 description: A phandle to the core analog power supply for PHY
107 description: A phandle to the core analog power supply for IC which generates reference clock
110 description: A phandle to the PCIe endpoint power supply
123 description: GPIO controlled connection to PERST# signal
127 description: GPIO controlled connection to WAKE# signal
149 - $ref: /schemas/pci/pci-bus.yaml#
158 - qcom,pcie-ipq8064v2
168 - const: dbi # DesignWare PCIe registers
169 - const: elbi # External local bus interface registers
170 - const: parf # Qualcomm specific registers
171 - const: config # PCIe configuration space
179 - qcom,pcie-ipq8074-gen3
187 - const: dbi # DesignWare PCIe registers
188 - const: elbi # External local bus interface registers
189 - const: atu # ATU address space
190 - const: parf # Qualcomm specific registers
191 - const: config # PCIe configuration space
209 - const: parf # Qualcomm specific registers
210 - const: dbi # DesignWare PCIe registers
211 - const: elbi # External local bus interface registers
212 - const: config # PCIe configuration space
213 - const: mhi # MHI registers
227 - qcom,pcie-sm8450-pcie0
228 - qcom,pcie-sm8450-pcie1
238 - const: parf # Qualcomm specific registers
239 - const: dbi # DesignWare PCIe registers
240 - const: elbi # External local bus interface registers
241 - const: atu # ATU address space
242 - const: config # PCIe configuration space
243 - const: mhi # MHI registers
252 - qcom,pcie-ipq8064v2
261 - const: core # Clocks the pcie hw block
262 - const: iface # Configuration AHB clock
263 - const: phy # Clocks the pcie PHY block
264 - const: aux # Clocks the pcie AUX block, not on apq8064
265 - const: ref # Clocks the pcie ref block, not on apq8064
272 - const: axi # AXI reset
273 - const: ahb # AHB reset
274 - const: por # POR reset
275 - const: pci # PCI reset
276 - const: phy # PHY reset
277 - const: ext # EXT reset, not on apq8064
296 - const: iface # Configuration AHB clock
297 - const: master_bus # Master AXI clock
298 - const: slave_bus # Slave AXI clock
299 - const: aux # Auxiliary (AUX) clock
304 - const: core # Core reset
319 - const: aux # Auxiliary (AUX) clock
320 - const: master_bus # Master AXI clock
321 - const: slave_bus # Slave AXI clock
327 - const: axi_m # AXI master reset
328 - const: axi_s # AXI slave reset
329 - const: pipe # PIPE reset
330 - const: axi_m_vmid # VMID reset
331 - const: axi_s_xpu # XPU reset
332 - const: parf # PARF reset
333 - const: phy # PHY reset
334 - const: axi_m_sticky # AXI sticky reset
335 - const: pipe_sticky # PIPE sticky reset
336 - const: pwr # PWR reset
337 - const: ahb # AHB reset
338 - const: phy_ahb # PHY AHB reset
353 - const: pipe # Pipe Clock driving internal logic
354 - const: aux # Auxiliary (AUX) clock
355 - const: cfg # Configuration clock
356 - const: bus_master # Master AXI clock
357 - const: bus_slave # Slave AXI clock
374 - const: iface # PCIe to SysNOC BIU clock
375 - const: axi_m # AXI Master clock
376 - const: axi_s # AXI Slave clock
377 - const: ahb # AHB clock
378 - const: aux # Auxiliary clock
384 - const: pipe # PIPE reset
385 - const: sleep # Sleep reset
386 - const: sticky # Core Sticky reset
387 - const: axi_m # AXI Master reset
388 - const: axi_s # AXI Slave reset
389 - const: ahb # AHB Reset
390 - const: axi_m_sticky # AXI Master Sticky reset
398 - qcom,pcie-ipq8074-gen3
406 - const: iface # PCIe to SysNOC BIU clock
407 - const: axi_m # AXI Master clock
408 - const: axi_s # AXI Slave clock
409 - const: axi_bridge # AXI bridge clock
416 - const: pipe # PIPE reset
417 - const: sleep # Sleep reset
418 - const: sticky # Core Sticky reset
419 - const: axi_m # AXI Master reset
420 - const: axi_s # AXI Slave reset
421 - const: ahb # AHB Reset
422 - const: axi_m_sticky # AXI Master Sticky reset
423 - const: axi_s_sticky # AXI Slave Sticky reset
438 - const: iface # AHB clock
439 - const: aux # Auxiliary clock
440 - const: master_bus # AXI Master clock
441 - const: slave_bus # AXI Slave clock
447 - const: axi_m # AXI Master reset
448 - const: axi_s # AXI Slave reset
449 - const: axi_m_sticky # AXI Master Sticky reset
450 - const: pipe_sticky # PIPE sticky reset
451 - const: pwr # PWR reset
452 - const: ahb # AHB reset
467 - const: pipe # PIPE clock
468 - const: pipe_mux # PIPE MUX
469 - const: phy_pipe # PIPE output clock
470 - const: ref # REFERENCE clock
471 - const: aux # Auxiliary clock
472 - const: cfg # Configuration clock
473 - const: bus_master # Master AXI clock
474 - const: bus_slave # Slave AXI clock
475 - const: slave_q2a # Slave Q2A clock
476 - const: tbu # PCIe TBU clock
477 - const: ddrss_sf_tbu # PCIe SF TBU clock
478 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
479 - const: aggre1 # Aggre NoC PCIe1 AXI clock
484 - const: pci # PCIe core reset
499 - const: pipe # PIPE clock
500 - const: aux # Auxiliary clock
501 - const: cfg # Configuration clock
502 - const: bus_master # Master AXI clock
503 - const: bus_slave # Slave AXI clock
504 - const: slave_q2a # Slave Q2A clock
505 - const: ref # REFERENCE clock
506 - const: tbu # PCIe TBU clock
511 - const: pci # PCIe core reset
521 # Unfortunately the "optional" ref clock is used in the middle of the list
528 - const: pipe # PIPE clock
529 - const: aux # Auxiliary clock
530 - const: cfg # Configuration clock
531 - const: bus_master # Master AXI clock
532 - const: bus_slave # Slave AXI clock
533 - const: slave_q2a # Slave Q2A clock
534 - const: ref # REFERENCE clock
535 - const: tbu # PCIe TBU clock
542 - const: pipe # PIPE clock
543 - const: aux # Auxiliary clock
544 - const: cfg # Configuration clock
545 - const: bus_master # Master AXI clock
546 - const: bus_slave # Slave AXI clock
547 - const: slave_q2a # Slave Q2A clock
548 - const: tbu # PCIe TBU clock
554 - const: pci # PCIe core reset
569 - const: pipe # PIPE clock
570 - const: aux # Auxiliary clock
571 - const: cfg # Configuration clock
572 - const: bus_master # Master AXI clock
573 - const: bus_slave # Slave AXI clock
574 - const: slave_q2a # Slave Q2A clock
575 - const: tbu # PCIe TBU clock
576 - const: ref # REFERENCE clock
581 - const: pci # PCIe core reset
591 # Unfortunately the "optional" ref clock is used in the middle of the list
598 - const: pipe # PIPE clock
599 - const: aux # Auxiliary clock
600 - const: cfg # Configuration clock
601 - const: bus_master # Master AXI clock
602 - const: bus_slave # Slave AXI clock
603 - const: slave_q2a # Slave Q2A clock
604 - const: ref # REFERENCE clock
605 - const: tbu # PCIe TBU clock
606 - const: ddrss_sf_tbu # PCIe SF TBU clock
613 - const: pipe # PIPE clock
614 - const: aux # Auxiliary clock
615 - const: cfg # Configuration clock
616 - const: bus_master # Master AXI clock
617 - const: bus_slave # Slave AXI clock
618 - const: slave_q2a # Slave Q2A clock
619 - const: tbu # PCIe TBU clock
620 - const: ddrss_sf_tbu # PCIe SF TBU clock
626 - const: pci # PCIe core reset
642 - const: aux # Auxiliary clock
643 - const: cfg # Configuration clock
644 - const: bus_master # Master AXI clock
645 - const: bus_slave # Slave AXI clock
646 - const: slave_q2a # Slave Q2A clock
647 - const: tbu # PCIe TBU clock
648 - const: ddrss_sf_tbu # PCIe SF TBU clock
649 - const: aggre1 # Aggre NoC PCIe1 AXI clock
650 - const: aggre0 # Aggre NoC PCIe0 AXI clock
655 - const: pci # PCIe core reset
662 - qcom,pcie-sm8450-pcie0
670 - const: pipe # PIPE clock
671 - const: pipe_mux # PIPE MUX
672 - const: phy_pipe # PIPE output clock
673 - const: ref # REFERENCE clock
674 - const: aux # Auxiliary clock
675 - const: cfg # Configuration clock
676 - const: bus_master # Master AXI clock
677 - const: bus_slave # Slave AXI clock
678 - const: slave_q2a # Slave Q2A clock
679 - const: ddrss_sf_tbu # PCIe SF TBU clock
680 - const: aggre0 # Aggre NoC PCIe0 AXI clock
681 - const: aggre1 # Aggre NoC PCIe1 AXI clock
686 - const: pci # PCIe core reset
693 - qcom,pcie-sm8450-pcie1
701 - const: pipe # PIPE clock
702 - const: pipe_mux # PIPE MUX
703 - const: phy_pipe # PIPE output clock
704 - const: ref # REFERENCE clock
705 - const: aux # Auxiliary clock
706 - const: cfg # Configuration clock
707 - const: bus_master # Master AXI clock
708 - const: bus_slave # Slave AXI clock
709 - const: slave_q2a # Slave Q2A clock
710 - const: ddrss_sf_tbu # PCIe SF TBU clock
711 - const: aggre1 # Aggre NoC PCIe1 AXI clock
716 - const: pci # PCIe core reset
732 - const: aux # Auxiliary clock
733 - const: cfg # Configuration clock
734 - const: bus_master # Master AXI clock
735 - const: bus_slave # Slave AXI clock
736 - const: slave_q2a # Slave Q2A clock
737 - const: ddrss_sf_tbu # PCIe SF TBU clock
738 - const: noc_aggr # Aggre NoC PCIe AXI clock
739 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
746 - const: pci # PCIe core reset
747 - const: link_down # PCIe link down reset
764 - const: aux # Auxiliary clock
765 - const: cfg # Configuration clock
766 - const: bus_master # Master AXI clock
767 - const: bus_slave # Slave AXI clock
768 - const: slave_q2a # Slave Q2A clock
769 - const: ddrss_sf_tbu # PCIe SF TBU clock
770 - const: noc_aggr_4 # NoC aggregate 4 clock
771 - const: noc_aggr_south_sf # NoC aggregate South SF clock
772 - const: cnoc_qx # Configuration NoC QX clock
777 - const: pci # PCIe core reset
792 - const: pipe # PIPE clock
793 - const: aux # Auxiliary clock
794 - const: cfg # Configuration clock
795 - const: bus_master # Master AXI clock
796 - const: bus_slave # Slave AXI clock
797 - const: slave_q2a # Slave Q2A clock
798 - const: sleep # PCIe Sleep clock
803 - const: pci # PCIe core reset
818 - const: aux # Auxiliary clock
819 - const: cfg # Configuration clock
820 - const: bus_master # Master AXI clock
821 - const: bus_slave # Slave AXI clock
822 - const: slave_q2a # Slave Q2A clock
827 - const: pci # PCIe core reset
851 - qcom,pcie-ipq8064v2
853 - qcom,pcie-ipq8074-gen3
884 - qcom,pcie-sm8450-pcie0
885 - qcom,pcie-sm8450-pcie1
937 - qcom,pcie-ipq8064-v2
939 - qcom,pcie-ipq8074-gen3
950 unevaluatedProperties: false
954 #include <dt-bindings/interrupt-controller/arm-gic.h>
956 compatible = "qcom,pcie-ipq8064";
957 reg = <0x1b500000 0x1000>,
960 <0x0ff00000 0x100000>;
961 reg-names = "dbi", "elbi", "parf", "config";
963 linux,pci-domain = <0>;
964 bus-range = <0x00 0xff>;
966 #address-cells = <3>;
968 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
969 <0x82000000 0 0 0x08000000 0 0x07e00000>;
970 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "msi";
972 #interrupt-cells = <1>;
973 interrupt-map-mask = <0 0 0 0x7>;
974 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
975 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
976 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
977 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
983 clock-names = "core", "iface", "phy", "aux", "ref";
990 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
991 pinctrl-0 = <&pcie_pins_default>;
992 pinctrl-names = "default";
993 vdda-supply = <&pm8921_s3>;
994 vdda_phy-supply = <&pm8921_lvs6>;
995 vdda_refclk-supply = <&ext_3p3v>;
998 #include <dt-bindings/interrupt-controller/arm-gic.h>
999 #include <dt-bindings/gpio/gpio.h>
1001 compatible = "qcom,pcie-apq8084";
1002 reg = <0xfc520000 0x2000>,
1003 <0xff000000 0x1000>,
1004 <0xff001000 0x1000>,
1005 <0xff002000 0x2000>;
1006 reg-names = "parf", "dbi", "elbi", "config";
1007 device_type = "pci";
1008 linux,pci-domain = <0>;
1009 bus-range = <0x00 0xff>;
1011 #address-cells = <3>;
1013 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
1014 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
1015 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "msi";
1017 #interrupt-cells = <1>;
1018 interrupt-map-mask = <0 0 0 0x7>;
1019 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
1020 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
1021 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
1022 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&gcc 324>,
1027 clock-names = "iface", "master_bus", "slave_bus", "aux";
1029 reset-names = "core";
1030 power-domains = <&gcc 1>;
1031 vdda-supply = <&pma8084_l3>;
1033 phy-names = "pciephy";
1034 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
1035 pinctrl-0 = <&pcie0_pins_default>;
1036 pinctrl-names = "default";