1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCIe Endpoint Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - const: qcom,sdx65-pcie-ep
20 - const: qcom,sdx55-pcie-ep
24 - description: Qualcomm-specific PARF configuration registers
25 - description: DesignWare PCIe registers
26 - description: External local bus interface registers
27 - description: Address Translation Unit (ATU) registers
28 - description: Memory region used to map remote RC address space
29 - description: BAR memory region
49 description: Reference to a syscon representing TCSR followed by the two
50 offsets within syscon for Perst enable and Perst separation
52 $ref: /schemas/types.yaml#/definitions/phandle-array
55 - description: Syscon to TCSR system registers
56 - description: Perst enable offset
57 - description: Perst separation enable offset
61 - description: PCIe Global interrupt
62 - description: PCIe Doorbell interrupt
70 description: GPIO used as PERST# input signal
74 description: GPIO used as WAKE# output signal
130 - description: PCIe Auxiliary clock
131 - description: PCIe CFG AHB clock
132 - description: PCIe Master AXI clock
133 - description: PCIe Slave AXI clock
134 - description: PCIe Slave Q2A AXI clock
135 - description: PCIe Sleep clock
136 - description: PCIe Reference clock
152 - qcom,sm8450-pcie-ep
157 - description: PCIe Auxiliary clock
158 - description: PCIe CFG AHB clock
159 - description: PCIe Master AXI clock
160 - description: PCIe Slave AXI clock
161 - description: PCIe Slave Q2A AXI clock
162 - description: PCIe Reference clock
163 - description: PCIe DDRSS SF TBU clock
164 - description: PCIe AGGRE NOC AXI clock
173 - const: ddrss_sf_tbu
174 - const: aggre_noc_axi
176 unevaluatedProperties: false
180 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
181 #include <dt-bindings/gpio/gpio.h>
182 #include <dt-bindings/interconnect/qcom,sdx55.h>
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
185 pcie_ep: pcie-ep@1c00000 {
186 compatible = "qcom,sdx55-pcie-ep";
187 reg = <0x01c00000 0x3000>,
193 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
196 clocks = <&gcc GCC_PCIE_AUX_CLK>,
197 <&gcc GCC_PCIE_CFG_AHB_CLK>,
198 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
199 <&gcc GCC_PCIE_SLV_AXI_CLK>,
200 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
201 <&gcc GCC_PCIE_SLEEP_CLK>,
202 <&gcc GCC_PCIE_0_CLKREF_CLK>;
203 clock-names = "aux", "cfg", "bus_master", "bus_slave",
204 "slave_q2a", "sleep", "ref";
206 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
208 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
210 interrupt-names = "global", "doorbell";
211 interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
212 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
213 interconnect-names = "pcie-mem", "cpu-pcie";
214 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
215 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
216 resets = <&gcc GCC_PCIE_BCR>;
217 reset-names = "core";
218 power-domains = <&gcc PCIE_GDSC>;
219 phys = <&pcie0_lane>;
220 phy-names = "pciephy";
221 max-link-speed = <3>;