1 NVIDIA Tegra PCIe controller
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
16 - reg-names: Must include the following entries:
17 "pads": PADS registers
19 "cs": configuration space region
20 - interrupts: A list of interrupt outputs of the controller. Must contain an
21 entry for each entry in the interrupt-names property.
22 - interrupt-names: Must include the following entries:
23 "intr": The Tegra interrupt that is asserted for controller interrupts
24 "msi": The Tegra interrupt that is asserted when an MSI is received
25 - bus-range: Range of bus numbers associated with this controller
26 - #address-cells: Address representation for root ports (must be 3)
27 - cell 0 specifies the bus and device numbers of the root port:
29 [15:11]: device number
30 - cell 1 denotes the upper 32 address bits and should be 0
31 - cell 2 contains the lower 32 address bits and is used to translate to the
33 - #size-cells: Size representation for root ports (must be 2)
34 - ranges: Describes the translation of addresses for root ports and standard
35 PCI regions. The entries must be 6 cells each, where the first three cells
36 correspond to the address as described for the #address-cells property
37 above, the fourth cell is the physical CPU address to translate to and the
38 fifth and six cells are as described for the #size-cells property above.
39 - The first two entries are expected to translate the addresses for the root
40 port registers, which are referenced by the assigned-addresses property of
41 the root port nodes (see below).
42 - The remaining entries setup the mapping for the standard I/O, memory and
43 prefetchable PCI regions. The first cell determines the type of region
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
48 Please refer to the standard PCI bus binding document for a more detailed
50 - #interrupt-cells: Size representation for interrupts (must be 1)
51 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
52 Please refer to the standard PCI bus binding document for a more detailed
54 - clocks: Must contain an entry for each entry in clock-names.
55 See ../clocks/clock-bindings.txt for details.
56 - clock-names: Must include the following entries:
60 - cml (not required for Tegra20)
61 - resets: Must contain an entry for each entry in reset-names.
62 See ../reset/reset.txt for details.
63 - reset-names: Must include the following entries:
69 - pinctrl-names: A list of pinctrl state names. Must contain the following
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
73 - pinctrl-0: phandle for the default/active state of pin configurations.
74 - pinctrl-1: phandle for the idle state of pin configurations.
76 Required properties on Tegra124 and later (deprecated):
77 - phys: Must contain an entry for each entry in phy-names.
78 - phy-names: Must include the following entries:
81 These properties are deprecated in favour of per-lane PHYs define in each of
82 the root ports (see below).
84 Power supplies for Tegra20:
85 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
86 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
87 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
89 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
91 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
93 Power supplies for Tegra30:
95 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
97 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
99 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
101 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
104 - If lanes 0 to 3 are used:
105 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
106 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
107 - If lanes 4 or 5 are used:
108 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
109 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
111 Power supplies for Tegra124:
113 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
114 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
115 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
117 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
120 Power supplies for Tegra210:
122 - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
123 clocks. Must supply 1.8 V.
124 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
125 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
128 Power supplies for Tegra186:
130 - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
131 - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
133 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
135 - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
138 Root ports are defined as subnodes of the PCIe controller node.
141 - device_type: Must be "pci"
142 - assigned-addresses: Address and size of the port configuration registers
143 - reg: PCI bus address of the root port
144 - #address-cells: Must be 3
145 - #size-cells: Must be 2
146 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
147 property is sufficient.
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
153 Required properties for Tegra124 and later:
154 - phys: Must contain an phandle to a PHY for each entry in phy-names.
155 - phy-names: Must include an entry for each active lane. Note that the number
156 of entries does not have to (though usually will) be equal to the specified
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
168 pcie-controller@80003000 {
169 compatible = "nvidia,tegra20-pcie";
171 reg = <0x80003000 0x00000800 /* PADS registers */
172 0x80003800 0x00000200 /* AFI registers */
173 0x90000000 0x10000000>; /* configuration space */
174 reg-names = "pads", "afi", "cs";
175 interrupts = <0 98 0x04 /* controller interrupt */
176 0 99 0x04>; /* MSI interrupt */
177 interrupt-names = "intr", "msi";
179 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 0>;
181 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
183 bus-range = <0x00 0xff>;
184 #address-cells = <3>;
187 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
188 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
189 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
190 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
191 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
193 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
194 clock-names = "pex", "afi", "pll_e";
195 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
196 reset-names = "pex", "afi", "pcie_x";
201 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
202 reg = <0x000800 0 0 0 0>;
205 #address-cells = <3>;
210 nvidia,num-lanes = <2>;
215 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
216 reg = <0x001000 0 0 0 0>;
219 #address-cells = <3>;
224 nvidia,num-lanes = <2>;
230 pcie-controller@80003000 {
233 vdd-supply = <&pci_vdd_reg>;
234 pex-clk-supply = <&pci_clk_reg>;
236 /* root port 00:01.0 */
240 /* bridge 01:00.0 (optional) */
242 reg = <0x010000 0 0 0 0>;
244 #address-cells = <3>;
249 /* endpoint 02:00.0 */
251 reg = <0x020000 0 0 0 0>;
257 Note that devices on the PCI bus are dynamically discovered using PCI's bus
258 enumeration and therefore don't need corresponding device nodes in DT. However
259 if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
260 device nodes need to be added in order to allow the bus' children to be
261 instantiated at the proper location in the operating system's device tree (as
262 illustrated by the optional nodes in the example above).
269 pcie-controller@3000 {
270 compatible = "nvidia,tegra30-pcie";
272 reg = <0x00003000 0x00000800 /* PADS registers */
273 0x00003800 0x00000200 /* AFI registers */
274 0x10000000 0x10000000>; /* configuration space */
275 reg-names = "pads", "afi", "cs";
276 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
277 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
278 interrupt-names = "intr", "msi";
280 #interrupt-cells = <1>;
281 interrupt-map-mask = <0 0 0 0>;
282 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
284 bus-range = <0x00 0xff>;
285 #address-cells = <3>;
288 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
289 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
290 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
291 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
292 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
293 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
295 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
296 <&tegra_car TEGRA30_CLK_AFI>,
297 <&tegra_car TEGRA30_CLK_PLL_E>,
298 <&tegra_car TEGRA30_CLK_CML0>;
299 clock-names = "pex", "afi", "pll_e", "cml";
300 resets = <&tegra_car 70>,
303 reset-names = "pex", "afi", "pcie_x";
308 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
309 reg = <0x000800 0 0 0 0>;
312 #address-cells = <3>;
316 nvidia,num-lanes = <2>;
321 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
322 reg = <0x001000 0 0 0 0>;
325 #address-cells = <3>;
329 nvidia,num-lanes = <2>;
334 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
335 reg = <0x001800 0 0 0 0>;
338 #address-cells = <3>;
342 nvidia,num-lanes = <2>;
348 pcie-controller@3000 {
351 avdd-pexa-supply = <&ldo1_reg>;
352 vdd-pexa-supply = <&ldo1_reg>;
353 avdd-pexb-supply = <&ldo1_reg>;
354 vdd-pexb-supply = <&ldo1_reg>;
355 avdd-pex-pll-supply = <&ldo1_reg>;
356 avdd-plle-supply = <&ldo1_reg>;
357 vddio-pex-ctl-supply = <&sys_3v3_reg>;
358 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
374 pcie-controller@1003000 {
375 compatible = "nvidia,tegra124-pcie";
377 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
378 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
379 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
380 reg-names = "pads", "afi", "cs";
381 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
382 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
383 interrupt-names = "intr", "msi";
385 #interrupt-cells = <1>;
386 interrupt-map-mask = <0 0 0 0>;
387 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
389 bus-range = <0x00 0xff>;
390 #address-cells = <3>;
393 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
394 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
395 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
396 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
397 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
399 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
400 <&tegra_car TEGRA124_CLK_AFI>,
401 <&tegra_car TEGRA124_CLK_PLL_E>,
402 <&tegra_car TEGRA124_CLK_CML0>;
403 clock-names = "pex", "afi", "pll_e", "cml";
404 resets = <&tegra_car 70>,
407 reset-names = "pex", "afi", "pcie_x";
412 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
413 reg = <0x000800 0 0 0 0>;
416 #address-cells = <3>;
420 nvidia,num-lanes = <2>;
425 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
426 reg = <0x001000 0 0 0 0>;
429 #address-cells = <3>;
433 nvidia,num-lanes = <1>;
439 pcie-controller@1003000 {
442 avddio-pex-supply = <&vdd_1v05_run>;
443 dvddio-pex-supply = <&vdd_1v05_run>;
444 avdd-pex-pll-supply = <&vdd_1v05_run>;
445 hvdd-pex-supply = <&vdd_3v3_lp0>;
446 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
447 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
448 avdd-pll-erefe-supply = <&avdd_1v05_run>;
452 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
453 phy-names = "pcie-0";
457 /* Gigabit Ethernet */
459 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
460 phy-names = "pcie-0";
470 pcie-controller@1003000 {
471 compatible = "nvidia,tegra210-pcie";
473 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
474 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
475 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
476 reg-names = "pads", "afi", "cs";
477 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
478 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
479 interrupt-names = "intr", "msi";
481 #interrupt-cells = <1>;
482 interrupt-map-mask = <0 0 0 0>;
483 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
485 bus-range = <0x00 0xff>;
486 #address-cells = <3>;
489 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
490 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
491 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
492 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
493 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
495 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
496 <&tegra_car TEGRA210_CLK_AFI>,
497 <&tegra_car TEGRA210_CLK_PLL_E>,
498 <&tegra_car TEGRA210_CLK_CML0>;
499 clock-names = "pex", "afi", "pll_e", "cml";
500 resets = <&tegra_car 70>,
503 reset-names = "pex", "afi", "pcie_x";
508 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
509 reg = <0x000800 0 0 0 0>;
512 #address-cells = <3>;
516 nvidia,num-lanes = <4>;
521 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
522 reg = <0x001000 0 0 0 0>;
525 #address-cells = <3>;
529 nvidia,num-lanes = <1>;
535 pcie-controller@1003000 {
538 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
539 hvddio-pex-supply = <&vdd_1v8>;
540 dvddio-pex-supply = <&vdd_pex_1v05>;
541 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
542 hvdd-pex-pll-e-supply = <&vdd_1v8>;
543 vddio-pex-ctl-supply = <&vdd_1v8>;
546 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
547 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
548 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
549 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
550 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
555 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
556 phy-names = "pcie-0";
567 compatible = "nvidia,tegra186-pcie";
568 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
570 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
571 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
572 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
573 reg-names = "pads", "afi", "cs";
575 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
576 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
577 interrupt-names = "intr", "msi";
579 #interrupt-cells = <1>;
580 interrupt-map-mask = <0 0 0 0>;
581 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
583 bus-range = <0x00 0xff>;
584 #address-cells = <3>;
587 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
588 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
589 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
590 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
591 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
592 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
594 clocks = <&bpmp TEGRA186_CLK_AFI>,
595 <&bpmp TEGRA186_CLK_PCIE>,
596 <&bpmp TEGRA186_CLK_PLLE>;
597 clock-names = "afi", "pex", "pll_e";
599 resets = <&bpmp TEGRA186_RESET_AFI>,
600 <&bpmp TEGRA186_RESET_PCIE>,
601 <&bpmp TEGRA186_RESET_PCIEXCLK>;
602 reset-names = "afi", "pex", "pcie_x";
608 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
609 reg = <0x000800 0 0 0 0>;
612 #address-cells = <3>;
616 nvidia,num-lanes = <2>;
621 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
622 reg = <0x001000 0 0 0 0>;
625 #address-cells = <3>;
629 nvidia,num-lanes = <1>;
634 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
635 reg = <0x001800 0 0 0 0>;
638 #address-cells = <3>;
642 nvidia,num-lanes = <1>;
651 dvdd-pex-supply = <&vdd_pex>;
652 hvdd-pex-pll-supply = <&vdd_1v8>;
653 hvdd-pex-supply = <&vdd_1v8>;
654 vddio-pexctl-aud-supply = <&vdd_1v8>;
657 nvidia,num-lanes = <4>;
662 nvidia,num-lanes = <0>;
667 nvidia,num-lanes = <1>;