1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
17 the controller instances are dual mode where in they can work either in
18 Root Port mode or Endpoint mode but one at a time.
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
27 - nvidia,tegra234-pcie
32 - description: controller's application logic registers
33 - description: configuration registers
34 - description: iATU and DMA registers. This is where the iATU (internal
35 Address Translation Unit) registers of the PCIe core are made
36 available for software access.
37 - description: aperture where the Root Port's own configuration
38 registers are available.
39 - description: aperture to access the configuration space through ECAM.
52 - description: controller interrupt
53 - description: MSI interrupt
62 - description: module clock
70 - description: APB bus interface reset
71 - description: module reset
97 A phandle to the node that controls power to the respective PCIe
98 controller and a specifier name for the PCIe controller.
100 Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
101 Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
105 - description: memory read client
106 - description: memory write client
110 - const: dma-mem # read
116 $ref: /schemas/types.yaml#/definitions/phandle-array
118 Must contain a pair of phandles to BPMP controller node followed by
119 controller ID. Following are the controller IDs for each controller:
146 - description: phandle to BPMP controller node
147 - description: PCIe controller ID
150 nvidia,update-fc-fixup:
152 This is a boolean property and needs to be present to improve performance
153 when a platform is designed in such a way that it satisfies at least one
154 of the following conditions thereby enabling Root Port to exchange
155 optimum number of FC (Flow Control) credits with downstream devices:
157 NOTE: This is applicable only for Tegra194.
159 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
160 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
161 a) speed is Gen-2 and MPS is 256B
162 b) speed is >= Gen-3 with any MPS
164 $ref: /schemas/types.yaml#/definitions/flag
167 description: Common Mode Restore Time for proper operation of ASPM to be
168 specified in microseconds
170 nvidia,aspm-pwr-on-t-us:
171 description: Power On time for proper operation of ASPM to be specified in
174 nvidia,aspm-l0s-entrance-latency-us:
175 description: ASPM L0s entrance latency to be specified in microseconds
177 vddio-pex-ctl-supply:
178 description: A phandle to the regulator supply for PCIe side band signals.
181 description: A phandle to the regulator node that supplies 3.3V to the slot
182 if the platform has one such slot, e.g., x16 slot owned by C5 controller
183 in p2972-0000 platform.
186 description: A phandle to the regulator node that supplies 12V to the slot
187 if the platform has one such slot, e.g., x16 slot owned by C5 controller
188 in p2972-0000 platform.
192 This boolean property needs to be present if the controller is
193 configured to operate in SRNS (Separate Reference Clocks with No
194 Spread-Spectrum Clocking). NOTE: This is applicable only for
197 $ref: /schemas/types.yaml#/definitions/flag
199 nvidia,enable-ext-refclk:
201 This boolean property needs to be present if the controller is
202 configured to use the reference clocking coming in from an external
203 clock source instead of using the internal clock source.
205 $ref: /schemas/types.yaml#/definitions/flag
208 - $ref: /schemas/pci/snps,dw-pcie.yaml#
214 - nvidia,tegra194-pcie
227 - nvidia,tegra234-pcie
235 unevaluatedProperties: false
247 - vddio-pex-ctl-supply
255 #include <dt-bindings/clock/tegra194-clock.h>
256 #include <dt-bindings/interrupt-controller/arm-gic.h>
257 #include <dt-bindings/power/tegra194-powergate.h>
258 #include <dt-bindings/reset/tegra194-reset.h>
261 #address-cells = <2>;
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
266 compatible = "nvidia,tegra194-pcie";
267 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
272 reg-names = "appl", "config", "atu_dma", "dbi";
274 #address-cells = <3>;
278 linux,pci-domain = <0>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
283 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
284 clock-names = "core";
286 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
287 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
288 reset-names = "apb", "core";
290 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
291 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
292 interrupt-names = "intr", "msi";
294 #interrupt-cells = <1>;
295 interrupt-map-mask = <0 0 0 0>;
296 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
298 nvidia,bpmp = <&bpmp 0>;
301 nvidia,aspm-cmrt-us = <60>;
302 nvidia,aspm-pwr-on-t-us = <20>;
303 nvidia,aspm-l0s-entrance-latency-us = <3>;
305 bus-range = <0x0 0xff>;
306 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
307 <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
308 <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
310 vddio-pex-ctl-supply = <&vdd_1v8ao>;
311 vpcie3v3-supply = <&vdd_3v3_pcie>;
312 vpcie12v-supply = <&vdd_12v_pcie>;
314 phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
316 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
321 #include <dt-bindings/clock/tegra234-clock.h>
322 #include <dt-bindings/interrupt-controller/arm-gic.h>
323 #include <dt-bindings/power/tegra234-powergate.h>
324 #include <dt-bindings/reset/tegra234-reset.h>
327 #address-cells = <2>;
329 ranges = <0x0 0x0 0x0 0x8 0x0>;
332 compatible = "nvidia,tegra234-pcie";
333 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
334 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
335 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
336 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
337 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
338 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
339 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
341 #address-cells = <3>;
346 linux,pci-domain = <4>;
348 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
349 clock-names = "core";
351 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
352 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
353 reset-names = "apb", "core";
355 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
356 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
357 interrupt-names = "intr", "msi";
359 #interrupt-cells = <1>;
360 interrupt-map-mask = <0 0 0 0>;
361 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
363 nvidia,bpmp = <&bpmp 4>;
365 nvidia,aspm-cmrt-us = <60>;
366 nvidia,aspm-pwr-on-t-us = <20>;
367 nvidia,aspm-l0s-entrance-latency-us = <3>;
369 bus-range = <0x0 0xff>;
370 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
371 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
372 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
374 vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
376 phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
378 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";