1 * Mobiveil AXI PCIe Root Port Bridge DT description
3 Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
4 has up to 8 outbound and inbound windows for the address translation.
7 - #address-cells: Address representation for root ports, set to <3>
8 - #size-cells: Size representation for root ports, set to <2>
9 - #interrupt-cells: specifies the number of cells needed to encode an
10 interrupt source. The value must be 1.
11 - compatible: Should contain "mbvl,gpex40-pcie"
12 - reg: Should contain PCIe registers location and length
13 "config_axi_slave": PCIe controller registers
14 "csr_axi_slave" : Bridge config registers
15 "gpio_slave" : GPIO registers to control slot power
16 "apb_csr" : MSI registers
18 - device_type: must be "pci"
19 - apio-wins : number of requested apio outbound windows
20 default 2 outbound windows are configured -
23 - ppio-wins : number of requested ppio inbound windows
24 default 1 inbound memory window is configured.
25 - bus-range: PCI bus numbers covered
26 - interrupt-controller: identifies the node as an interrupt controller
27 - #interrupt-cells: specifies the number of cells needed to encode an
28 interrupt source. The value must be 1.
29 - interrupts: The interrupt line of the PCIe controller
30 last cell of this field is set to 4 to
31 denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
33 interrupt-map: standard PCI properties to define the mapping of the
34 PCI interface to interrupt numbers.
35 - ranges: ranges for the PCI memory regions (I/O space region is not
36 supported by hardware)
37 Please refer to the standard PCI bus binding document for a more
43 pcie0: pcie@a0000000 {
46 compatible = "mbvl,gpex40-pcie";
47 reg = <0xa0000000 0x00001000>,
48 <0xb0000000 0x00010000>,
49 <0xff000000 0x00200000>,
50 <0xb0010000 0x00001000>;
51 reg-names = "config_axi_slave",
58 bus-range = <0x00000000 0x000000ff>;
60 interrupt-parent = <&gic>;
61 #interrupt-cells = <1>;
62 interrupts = < 0 89 4 >;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0 0 0 0 &pci_express 0>,
65 <0 0 0 1 &pci_express 1>,
66 <0 0 0 2 &pci_express 2>,
67 <0 0 0 3 &pci_express 3>;
68 ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;