1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 PCIe controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
17 - $ref: /schemas/pci/pci-bus.yaml#
21 const: mediatek,mt7621-pci
25 - description: host-pci bridge registers
26 - description: pcie port 0 RC control registers
27 - description: pcie port 1 RC control registers
28 - description: pcie port 2 RC control registers
36 $ref: /schemas/pci/pci-bus.yaml#
49 pattern: '^pcie-phy[0-2]$'
61 unevaluatedProperties: false
72 unevaluatedProperties: false
76 #include <dt-bindings/gpio/gpio.h>
77 #include <dt-bindings/interrupt-controller/mips-gic.h>
80 compatible = "mediatek,mt7621-pci";
81 reg = <0x1e140000 0x100>,
88 pinctrl-names = "default";
89 pinctrl-0 = <&pcie_pins>;
91 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
92 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
93 #interrupt-cells = <1>;
94 interrupt-map-mask = <0xF800 0 0 0>;
95 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
97 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
98 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
101 reg = <0x0000 0 0 0 0>;
102 #address-cells = <3>;
105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0 0 0 0>;
107 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
108 resets = <&rstctrl 24>;
109 clocks = <&clkctrl 24>;
110 phys = <&pcie0_phy 1>;
111 phy-names = "pcie-phy0";
116 reg = <0x0800 0 0 0 0>;
117 #address-cells = <3>;
120 #interrupt-cells = <1>;
121 interrupt-map-mask = <0 0 0 0>;
122 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
123 resets = <&rstctrl 25>;
124 clocks = <&clkctrl 25>;
125 phys = <&pcie0_phy 1>;
126 phy-names = "pcie-phy1";
131 reg = <0x1000 0 0 0 0>;
132 #address-cells = <3>;
135 #interrupt-cells = <1>;
136 interrupt-map-mask = <0 0 0 0>;
137 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
138 resets = <&rstctrl 26>;
139 clocks = <&clkctrl 26>;
140 phys = <&pcie2_phy 0>;
141 phy-names = "pcie-phy2";