Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MediaTek MT7621 PCIe controller
   8
   9 maintainers:
  10   - Sergio Paracuellos <sergio.paracuellos@gmail.com>
  11
  12 description: |+
  13   MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
  14   with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
  15
  16 allOf:
  17   - $ref: /schemas/pci/pci-bus.yaml#
  18
  19 properties:
  20   compatible:
  21     const: mediatek,mt7621-pci
  22
  23   reg:
  24     items:
  25       - description: host-pci bridge registers
  26       - description: pcie port 0 RC control registers
  27       - description: pcie port 1 RC control registers
  28       - description: pcie port 2 RC control registers
  29
  30   ranges:
  31     maxItems: 2
  32
  33 patternProperties:
  34   '^pcie@[0-2],0$':
  35     type: object
  36     $ref: /schemas/pci/pci-bus.yaml#
  37
  38     properties:
  39       resets:
  40         maxItems: 1
  41
  42       clocks:
  43         maxItems: 1
  44
  45       phys:
  46         maxItems: 1
  47
  48       phy-names:
  49         pattern: '^pcie-phy[0-2]$'
  50
  51     required:
  52       - "#interrupt-cells"
  53       - interrupt-map-mask
  54       - interrupt-map
  55       - resets
  56       - clocks
  57       - phys
  58       - phy-names
  59       - ranges
  60
  61     unevaluatedProperties: false
  62
  63 required:
  64   - compatible
  65   - reg
  66   - ranges
  67   - "#interrupt-cells"
  68   - interrupt-map-mask
  69   - interrupt-map
  70   - reset-gpios
  71
  72 unevaluatedProperties: false
  73
  74 examples:
  75   - |
  76     #include <dt-bindings/gpio/gpio.h>
  77     #include <dt-bindings/interrupt-controller/mips-gic.h>
  78
  79     pcie: pcie@1e140000 {
  80         compatible = "mediatek,mt7621-pci";
  81         reg = <0x1e140000 0x100>,
  82               <0x1e142000 0x100>,
  83               <0x1e143000 0x100>,
  84               <0x1e144000 0x100>;
  85
  86         #address-cells = <3>;
  87         #size-cells = <2>;
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pcie_pins>;
  90         device_type = "pci";
  91         ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>,  /* pci memory */
  92                  <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>;  /* io space */
  93         #interrupt-cells = <1>;
  94         interrupt-map-mask = <0xF800 0 0 0>;
  95         interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
  96                         <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
  97                         <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
  98         reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
  99
 100         pcie@0,0 {
 101             reg = <0x0000 0 0 0 0>;
 102             #address-cells = <3>;
 103             #size-cells = <2>;
 104             device_type = "pci";
 105             #interrupt-cells = <1>;
 106             interrupt-map-mask = <0 0 0 0>;
 107             interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
 108             resets = <&rstctrl 24>;
 109             clocks = <&clkctrl 24>;
 110             phys = <&pcie0_phy 1>;
 111             phy-names = "pcie-phy0";
 112             ranges;
 113         };
 114
 115         pcie@1,0 {
 116             reg = <0x0800 0 0 0 0>;
 117             #address-cells = <3>;
 118             #size-cells = <2>;
 119             device_type = "pci";
 120             #interrupt-cells = <1>;
 121             interrupt-map-mask = <0 0 0 0>;
 122             interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
 123             resets = <&rstctrl 25>;
 124             clocks = <&clkctrl 25>;
 125             phys = <&pcie0_phy 1>;
 126             phy-names = "pcie-phy1";
 127             ranges;
 128         };
 129
 130         pcie@2,0 {
 131             reg = <0x1000 0 0 0 0>;
 132             #address-cells = <3>;
 133             #size-cells = <2>;
 134             device_type = "pci";
 135             #interrupt-cells = <1>;
 136             interrupt-map-mask = <0 0 0 0>;
 137             interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 138             resets = <&rstctrl 26>;
 139             clocks = <&clkctrl 26>;
 140             phys = <&pcie2_phy 0>;
 141             phy-names = "pcie-phy2";
 142             ranges;
 143         };
 144     };
 145 ...