1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
16 inherits common properties defined in
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - hisilicon,kirin960-pcie
27 - hisilicon,kirin970-pcie
31 Should contain dbi, apb, config registers location and length.
32 For hisilicon,kirin960-pcie, it should also contain phy.
40 hisilicon,clken-gpios:
42 Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and
50 unevaluatedProperties: false
54 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 #include <dt-bindings/clock/hi3660-clock.h>
56 #include <dt-bindings/clock/hi3670-clock.h>
63 compatible = "hisilicon,kirin960-pcie";
64 reg = <0x0 0xf4000000 0x0 0x1000>,
65 <0x0 0xff3fe000 0x0 0x1000>,
66 <0x0 0xf3f20000 0x0 0x40000>,
67 <0x0 0xf5000000 0x0 0x2000>;
68 reg-names = "dbi", "apb", "phy", "config";
69 bus-range = <0x0 0xff>;
73 ranges = <0x02000000 0x0 0x00000000
77 #interrupt-cells = <1>;
78 interrupts = <0 283 4>;
79 interrupt-names = "msi";
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
82 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
83 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
84 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
86 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
87 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
88 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
89 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
90 clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
91 "pcie_apb_sys", "pcie_aclk";
95 compatible = "hisilicon,kirin970-pcie";
96 reg = <0x0 0xf4000000 0x0 0x1000000>,
97 <0x0 0xfc180000 0x0 0x1000>,
98 <0x0 0xf5000000 0x0 0x2000>;
99 reg-names = "dbi", "apb", "config";
100 bus-range = <0x0 0xff>;
101 #address-cells = <3>;
105 ranges = <0x02000000 0x0 0x00000000
109 #interrupt-cells = <1>;
110 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
111 interrupt-names = "msi";
112 interrupt-map-mask = <0 0 0 7>;
113 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
114 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
115 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
116 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
117 reset-gpios = <&gpio7 0 0>;
118 hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
119 pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
121 compatible = "pciclass,0604";
123 #address-cells = <3>;
127 pcie@0,0 { // Lane 0: upstream
129 compatible = "pciclass,0604";
131 #address-cells = <3>;
135 pcie@1,0 { // Lane 4: M.2
136 reg = <0x0800 0 0 0 0>;
137 compatible = "pciclass,0604";
139 reset-gpios = <&gpio3 1 0>;
140 #address-cells = <3>;
145 pcie@5,0 { // Lane 5: Mini PCIe
146 reg = <0x2800 0 0 0 0>;
147 compatible = "pciclass,0604";
149 reset-gpios = <&gpio27 4 0 >;
150 #address-cells = <3>;
155 pcie@7,0 { // Lane 6: Ethernet
156 reg = <0x03800 0 0 0 0>;
157 compatible = "pciclass,0604";
159 reset-gpios = <&gpio25 2 0 >;
160 #address-cells = <3>;