1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe host controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16 The controller instances are dual mode where in they can work either in
17 Root Port mode or Endpoint mode but one at a time.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
35 - description: Data Bus Interface (DBI) registers.
36 - description: PCIe configuration space region.
46 - description: PCIe bridge clock.
47 - description: PCIe bus clock.
48 - description: PCIe PHY clock.
49 - description: Additional required clock entry for imx6sx-pcie,
50 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
58 - description: builtin MSI controller.
65 description: Should specify the GPIO for controlling the PCI bus device
66 reset signal. It's not polarity aware and defaults to active-low reset
67 sequence (L=reset state, H=operation state) (optional required).
69 reset-gpio-active-high:
70 description: If present then the reset sequence using the GPIO
71 specified in the "reset-gpio" property is reversed (H=reset state,
72 L=operation state) (optional required).
91 - $ref: /schemas/pci/snps,dw-pcie.yaml#
92 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
107 - const: pcie_inbound_axi
158 unevaluatedProperties: false
162 #include <dt-bindings/clock/imx6qdl-clock.h>
163 #include <dt-bindings/interrupt-controller/arm-gic.h>
166 compatible = "fsl,imx6q-pcie";
167 reg = <0x01ffc000 0x04000>,
168 <0x01f00000 0x80000>;
169 reg-names = "dbi", "config";
170 #address-cells = <3>;
173 bus-range = <0x00 0xff>;
174 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
175 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
177 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "msi";
179 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 0x7>;
181 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
184 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
186 <&clks IMX6QDL_CLK_LVDS1_GATE>,
187 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
188 clock-names = "pcie", "pcie_bus", "pcie_phy";