Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale i.MX6 PCIe Endpoint controller
   8
   9 maintainers:
  10   - Lucas Stach <l.stach@pengutronix.de>
  11   - Richard Zhu <hongxing.zhu@nxp.com>
  12
  13 description: |+
  14   This PCIe controller is based on the Synopsys DesignWare PCIe IP and
  15   thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
  16   The controller instances are dual mode where in they can work either in
  17   Root Port mode or Endpoint mode but one at a time.
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - fsl,imx8mm-pcie-ep
  23       - fsl,imx8mq-pcie-ep
  24       - fsl,imx8mp-pcie-ep
  25
  26   reg:
  27     minItems: 2
  28
  29   reg-names:
  30     items:
  31       - const: dbi
  32       - const: addr_space
  33
  34   clocks:
  35     minItems: 3
  36     items:
  37       - description: PCIe bridge clock.
  38       - description: PCIe bus clock.
  39       - description: PCIe PHY clock.
  40       - description: Additional required clock entry for imx6sx-pcie,
  41            imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
  42
  43   clock-names:
  44     minItems: 3
  45     maxItems: 4
  46
  47   interrupts:
  48     items:
  49       - description: builtin eDMA interrupter.
  50
  51   interrupt-names:
  52     items:
  53       - const: dma
  54
  55 required:
  56   - compatible
  57   - reg
  58   - reg-names
  59   - interrupts
  60   - interrupt-names
  61
  62 allOf:
  63   - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
  64   - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
  65   - if:
  66       properties:
  67         compatible:
  68           enum:
  69             - fsl,imx8mq-pcie-ep
  70     then:
  71       properties:
  72         clocks:
  73           minItems: 4
  74         clock-names:
  75           items:
  76             - const: pcie
  77             - const: pcie_bus
  78             - const: pcie_phy
  79             - const: pcie_aux
  80     else:
  81       properties:
  82         clocks:
  83           maxItems: 3
  84         clock-names:
  85           items:
  86             - const: pcie
  87             - const: pcie_bus
  88             - const: pcie_aux
  89
  90
  91 unevaluatedProperties: false
  92
  93 examples:
  94   - |
  95     #include <dt-bindings/clock/imx8mp-clock.h>
  96     #include <dt-bindings/power/imx8mp-power.h>
  97     #include <dt-bindings/reset/imx8mp-reset.h>
  98     #include <dt-bindings/interrupt-controller/arm-gic.h>
  99
 100     pcie_ep: pcie-ep@33800000 {
 101       compatible = "fsl,imx8mp-pcie-ep";
 102       reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
 103       reg-names = "dbi", "addr_space";
 104       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 105                <&clk IMX8MP_CLK_HSIO_AXI>,
 106                <&clk IMX8MP_CLK_PCIE_ROOT>;
 107       clock-names = "pcie", "pcie_bus", "pcie_aux";
 108       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 109       assigned-clock-rates = <10000000>;
 110       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
 111       num-lanes = <1>;
 112       interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
 113       interrupt-names = "dma";
 114       fsl,max-link-speed = <3>;
 115       power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
 116       resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
 117                <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
 118       reset-names = "apps", "turnoff";
 119       phys = <&pcie_phy>;
 120       phy-names = "pcie-phy";
 121       num-ib-windows = <4>;
 122       num-ob-windows = <4>;
 123     };