1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
20 # for the first generation of PAXB based controller, used in SoCs
21 # including NSP, Cygnus, NS2, and Pegasus
23 # for the second generation of PAXB-based controllers, used in
25 - brcm,iproc-pcie-paxb-v2
26 # For the first generation of PAXC based controller, used in NS2
27 - brcm,iproc-pcie-paxc
28 # For the second generation of PAXC based controller, used in Stingray
29 - brcm,iproc-pcie-paxc-v2
34 Base address and length of the PCIe controller I/O register space
40 Ranges for the PCI memory and I/O regions
54 Some iProc SoCs do not have the outbound address mapping done by the
55 ASIC after power on reset. In this case, SW needs to configure it
57 brcm,pcie-ob-axi-offset:
58 $ref: /schemas/types.yaml#/definitions/uint32
60 The offset from the AXI address to the internal address used by the
61 iProc PCIe core (not the PCIe address)
65 $ref: /schemas/interrupt-controller/msi-controller.yaml#
66 unevaluatedProperties: false
71 - const: brcm,iproc-msi
79 Needs to be present for some older iProc platforms that require the
80 interrupt enable registers to be set explicitly to enable MSI
85 brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
86 brcm,pcie-msi-inten: [msi-controller]
104 unevaluatedProperties: false
108 #include <dt-bindings/interrupt-controller/arm-gic.h>
110 gic: interrupt-controller {
111 interrupt-controller;
112 #interrupt-cells = <3>;
116 compatible = "brcm,iproc-pcie";
117 reg = <0x18012000 0x1000>;
119 #interrupt-cells = <1>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
123 linux,pci-domain = <0>;
125 bus-range = <0x00 0xff>;
127 #address-cells = <3>;
130 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
131 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
134 phy-names = "pcie-phy";
137 brcm,pcie-ob-axi-offset = <0x00000000>;
139 msi-parent = <&msi0>;
141 /* iProc event queue based MSI */
143 compatible = "brcm,iproc-msi";
145 interrupt-parent = <&gic>;
146 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
147 <GIC_SPI 97 IRQ_TYPE_NONE>,
148 <GIC_SPI 98 IRQ_TYPE_NONE>,
149 <GIC_SPI 99 IRQ_TYPE_NONE>;
154 compatible = "brcm,iproc-pcie";
155 reg = <0x18013000 0x1000>;
157 #interrupt-cells = <1>;
158 interrupt-map-mask = <0 0 0 0>;
159 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
161 linux,pci-domain = <1>;
163 bus-range = <0x00 0xff>;
165 #address-cells = <3>;
168 ranges = <0x81000000 0 0 0x48000000 0 0x00010000>,
169 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
172 phy-names = "pcie-phy";