1 * Altera PCIe controller
4 - compatible : should contain "altr,pcie-root-port-1.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 - reg-names: must include the following entries:
7 "Txs": TX slave port region
8 "Cra": Control register access region
9 - interrupts: specifies the interrupt source of the parent interrupt
10 controller. The format of the interrupt specifier depends
11 on the parent interrupt controller.
12 - device_type: must be "pci"
13 - #address-cells: set to <3>
14 - #size-cells: set to <2>
15 - #interrupt-cells: set to <1>
16 - ranges: describes the translation of addresses for root ports and
18 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
19 mapping of the PCIe interface to interrupt numbers.
22 - msi-parent: Link to the hardware entity that serves as the MSI controller
23 for this PCIe controller.
24 - bus-range: PCI bus numbers covered
27 pcie_0: pcie@c00000000 {
28 compatible = "altr,pcie-root-port-1.0";
29 reg = <0xc0000000 0x20000000>,
30 <0xff220000 0x00004000>;
31 reg-names = "Txs", "Cra";
32 interrupt-parent = <&hps_0_arm_gic_0>;
33 interrupts = <0 40 4>;
35 #interrupt-cells = <1>;
36 bus-range = <0x0 0xFF>;
38 msi-parent = <&msi_to_gic_gen_0>;
41 interrupt-map-mask = <0 0 0 7>;
42 interrupt-map = <0 0 0 1 &pcie_0 1>,
46 ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
47 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;