Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. NVMEM OPP
   8
   9 maintainers:
  10   - Ilia Lin <ilia.lin@kernel.org>
  11
  12 allOf:
  13   - $ref: opp-v2-base.yaml#
  14
  15 description: |
  16   In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
  17   the CPU frequencies subset and voltage value of each OPP varies based on
  18   the silicon variant in use.
  19   Qualcomm Technologies, Inc. Process Voltage Scaling Tables
  20   defines the voltage and frequency value based on the speedbin blown in
  21   the efuse combination.
  22   The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
  23   the OPP framework with required information (existing HW bitmap).
  24   This is used to determine the voltage and frequency value for each OPP of
  25   operating-points-v2 table when it is parsed by the OPP framework.
  26
  27 properties:
  28   compatible:
  29     enum:
  30       - operating-points-v2-krait-cpu
  31       - operating-points-v2-kryo-cpu
  32
  33   nvmem-cells:
  34     description: |
  35       A phandle pointing to a nvmem-cells node representing the
  36       efuse registers that has information about the
  37       speedbin that is used to select the right frequency/voltage
  38       value pair.
  39
  40   opp-shared: true
  41
  42 patternProperties:
  43   '^opp-?[0-9]+$':
  44     type: object
  45     additionalProperties: false
  46
  47     properties:
  48       opp-hz: true
  49
  50       opp-microvolt: true
  51
  52       opp-peak-kBps: true
  53
  54       opp-supported-hw:
  55         description: |
  56           A single 32 bit bitmap value, representing compatible HW.
  57           Bitmap for MSM8996 format:
  58           0:  MSM8996, speedbin 0
  59           1:  MSM8996, speedbin 1
  60           2:  MSM8996, speedbin 2
  61           3:  MSM8996, speedbin 3
  62           4-31:  unused
  63
  64           Bitmap for MSM8996SG format (speedbin shifted of 4 left):
  65           0-3:  unused
  66           4:  MSM8996SG, speedbin 0
  67           5:  MSM8996SG, speedbin 1
  68           6:  MSM8996SG, speedbin 2
  69           7-31:  unused
  70
  71           Bitmap for IPQ806x SoC:
  72           0:  IPQ8062
  73           1:  IPQ8064/IPQ8066/IPQ8068
  74           2:  IPQ8065/IPQ8069
  75           3-31:  unused
  76
  77           Other platforms use bits directly corresponding to speedbin index.
  78
  79       clock-latency-ns: true
  80
  81       required-opps: true
  82
  83     patternProperties:
  84       '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
  85
  86     required:
  87       - opp-hz
  88
  89 required:
  90   - compatible
  91
  92 if:
  93   required:
  94     - nvmem-cells
  95 then:
  96   patternProperties:
  97     '^opp-?[0-9]+$':
  98       required:
  99         - opp-supported-hw
 100
 101 additionalProperties: false
 102
 103 examples:
 104   - |
 105     / {
 106         model = "Qualcomm Technologies, Inc. DB820c";
 107         compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
 108         #address-cells = <2>;
 109         #size-cells = <2>;
 110
 111         cpus {
 112             #address-cells = <2>;
 113             #size-cells = <0>;
 114
 115             CPU0: cpu@0 {
 116                 device_type = "cpu";
 117                 compatible = "qcom,kryo";
 118                 reg = <0x0 0x0>;
 119                 enable-method = "psci";
 120                 cpu-idle-states = <&CPU_SLEEP_0>;
 121                 capacity-dmips-mhz = <1024>;
 122                 clocks = <&kryocc 0>;
 123                 operating-points-v2 = <&cluster0_opp>;
 124                 power-domains = <&cpr>;
 125                 power-domain-names = "cpr";
 126                 #cooling-cells = <2>;
 127                 next-level-cache = <&L2_0>;
 128                 L2_0: l2-cache {
 129                     compatible = "cache";
 130                     cache-level = <2>;
 131                     cache-unified;
 132                 };
 133             };
 134
 135             CPU1: cpu@1 {
 136                 device_type = "cpu";
 137                 compatible = "qcom,kryo";
 138                 reg = <0x0 0x1>;
 139                 enable-method = "psci";
 140                 cpu-idle-states = <&CPU_SLEEP_0>;
 141                 capacity-dmips-mhz = <1024>;
 142                 clocks = <&kryocc 0>;
 143                 operating-points-v2 = <&cluster0_opp>;
 144                 power-domains = <&cpr>;
 145                 power-domain-names = "cpr";
 146                 #cooling-cells = <2>;
 147                 next-level-cache = <&L2_0>;
 148             };
 149
 150             CPU2: cpu@100 {
 151                 device_type = "cpu";
 152                 compatible = "qcom,kryo";
 153                 reg = <0x0 0x100>;
 154                 enable-method = "psci";
 155                 cpu-idle-states = <&CPU_SLEEP_0>;
 156                 capacity-dmips-mhz = <1024>;
 157                 clocks = <&kryocc 1>;
 158                 operating-points-v2 = <&cluster1_opp>;
 159                 power-domains = <&cpr>;
 160                 power-domain-names = "cpr";
 161                 #cooling-cells = <2>;
 162                 next-level-cache = <&L2_1>;
 163                 L2_1: l2-cache {
 164                     compatible = "cache";
 165                     cache-level = <2>;
 166                     cache-unified;
 167                 };
 168             };
 169
 170             CPU3: cpu@101 {
 171                 device_type = "cpu";
 172                 compatible = "qcom,kryo";
 173                 reg = <0x0 0x101>;
 174                 enable-method = "psci";
 175                 cpu-idle-states = <&CPU_SLEEP_0>;
 176                 capacity-dmips-mhz = <1024>;
 177                 clocks = <&kryocc 1>;
 178                 operating-points-v2 = <&cluster1_opp>;
 179                 power-domains = <&cpr>;
 180                 power-domain-names = "cpr";
 181                 #cooling-cells = <2>;
 182                 next-level-cache = <&L2_1>;
 183             };
 184
 185             cpu-map {
 186                 cluster0 {
 187                     core0 {
 188                         cpu = <&CPU0>;
 189                     };
 190
 191                     core1 {
 192                         cpu = <&CPU1>;
 193                     };
 194                 };
 195
 196                 cluster1 {
 197                     core0 {
 198                         cpu = <&CPU2>;
 199                     };
 200
 201                     core1 {
 202                         cpu = <&CPU3>;
 203                     };
 204                 };
 205             };
 206         };
 207
 208         cluster0_opp: opp-table-0 {
 209             compatible = "operating-points-v2-kryo-cpu";
 210             nvmem-cells = <&speedbin_efuse>;
 211             opp-shared;
 212
 213             opp-307200000 {
 214                 opp-hz = /bits/ 64 <307200000>;
 215                 opp-microvolt = <905000 905000 1140000>;
 216                 opp-supported-hw = <0x7>;
 217                 clock-latency-ns = <200000>;
 218                 required-opps = <&cpr_opp1>;
 219             };
 220             opp-1401600000 {
 221                 opp-hz = /bits/ 64 <1401600000>;
 222                 opp-microvolt = <1140000 905000 1140000>;
 223                 opp-supported-hw = <0x5>;
 224                 clock-latency-ns = <200000>;
 225                 required-opps = <&cpr_opp2>;
 226             };
 227             opp-1593600000 {
 228                 opp-hz = /bits/ 64 <1593600000>;
 229                 opp-microvolt = <1140000 905000 1140000>;
 230                 opp-supported-hw = <0x1>;
 231                 clock-latency-ns = <200000>;
 232                 required-opps = <&cpr_opp3>;
 233             };
 234         };
 235
 236         cluster1_opp: opp-table-1 {
 237             compatible = "operating-points-v2-kryo-cpu";
 238             nvmem-cells = <&speedbin_efuse>;
 239             opp-shared;
 240
 241             opp-307200000 {
 242                 opp-hz = /bits/ 64 <307200000>;
 243                 opp-microvolt = <905000 905000 1140000>;
 244                 opp-supported-hw = <0x7>;
 245                 clock-latency-ns = <200000>;
 246                 required-opps = <&cpr_opp1>;
 247             };
 248             opp-1804800000 {
 249                 opp-hz = /bits/ 64 <1804800000>;
 250                 opp-microvolt = <1140000 905000 1140000>;
 251                 opp-supported-hw = <0x6>;
 252                 clock-latency-ns = <200000>;
 253                 required-opps = <&cpr_opp4>;
 254             };
 255             opp-1900800000 {
 256                 opp-hz = /bits/ 64 <1900800000>;
 257                 opp-microvolt = <1140000 905000 1140000>;
 258                 opp-supported-hw = <0x4>;
 259                 clock-latency-ns = <200000>;
 260                 required-opps = <&cpr_opp5>;
 261             };
 262             opp-2150400000 {
 263                 opp-hz = /bits/ 64 <2150400000>;
 264                 opp-microvolt = <1140000 905000 1140000>;
 265                 opp-supported-hw = <0x1>;
 266                 clock-latency-ns = <200000>;
 267                 required-opps = <&cpr_opp6>;
 268             };
 269         };
 270
 271         /* Dummy opp table to give example for named opp-microvolt */
 272         opp-table-2 {
 273             compatible = "operating-points-v2-krait-cpu";
 274             nvmem-cells = <&speedbin_efuse>;
 275
 276             opp-384000000 {
 277                 opp-hz = /bits/ 64 <384000000>;
 278                 opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
 279                 opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
 280                 opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
 281                 opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
 282                 opp-supported-hw = <0x7>;
 283                 clock-latency-ns = <100000>;
 284             };
 285         };
 286
 287         smem {
 288             compatible = "qcom,smem";
 289             memory-region = <&smem_mem>;
 290             hwlocks = <&tcsr_mutex 3>;
 291         };
 292
 293         soc {
 294             #address-cells = <1>;
 295             #size-cells = <1>;
 296
 297             qfprom: qfprom@74000 {
 298                 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
 299                 reg = <0x00074000 0x8ff>;
 300                 #address-cells = <1>;
 301                 #size-cells = <1>;
 302
 303                 speedbin_efuse: speedbin@133 {
 304                     reg = <0x133 0x1>;
 305                     bits = <5 3>;
 306                 };
 307             };
 308         };
 309     };