1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11 provides connectivity to an external ethernet PHY supporting different
12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
33 Address and length of the IO space, as well as the address
34 and length of the AXI DMA controller IO space, unless
35 axistream-connected is specified, in which case the reg
36 attribute of the node referenced by it is used.
41 - description: Ethernet core interrupt
42 - description: Tx DMA interrupt
43 - description: Rx DMA interrupt
45 Ethernet core interrupt is optional. If axistream-connected property is
46 present DMA node should contains TX/RX DMA interrupts else DMA interrupt
47 resources are mentioned on ethernet node.
54 Set to allocated memory buffer for Rx/Tx in the hardware.
55 $ref: /schemas/types.yaml#/definitions/uint32
67 Do not use, but still accepted in preference to phy-mode.
69 $ref: /schemas/types.yaml#/definitions/uint32
73 TX checksum offload. 0 or empty for disabling TX checksum offload,
74 1 to enable partial TX checksum offload and 2 to enable full TX
76 $ref: /schemas/types.yaml#/definitions/uint32
81 RX checksum offload. 0 or empty for disabling RX checksum offload,
82 1 to enable partial RX checksum offload and 2 to enable full RX
84 $ref: /schemas/types.yaml#/definitions/uint32
90 Indicate the Ethernet core is configured to support both 1000BaseX and
91 SGMII modes. If set, the phy-mode should be set to match the mode
92 selected on core reset (i.e. by the basex_or_sgmii core input line).
96 - description: Clock for AXI register slave interface.
97 - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
98 - description: Ethernet reference clock, used by signal delay primitives
100 - description: MGT reference clock (used by optional internal PCS/PMA PHY)
104 - const: s_axi_lite_clk
110 $ref: /schemas/types.yaml#/definitions/phandle
111 description: Phandle of AXI DMA controller which contains the resources
112 used by this device. If this is specified, the DMA-related resources
113 from that device (DMA registers and DMA TX/RX interrupts) rather than
114 this one will be used.
120 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
121 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
122 and "phy-handle" should point to an external PHY if exists.
133 - $ref: /schemas/net/ethernet-controller.yaml#
135 additionalProperties: false
139 axi_ethernet_eth: ethernet@40c00000 {
140 compatible = "xlnx,axi-ethernet-1.00.a";
141 interrupts = <2 0 1>;
142 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
143 clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
145 reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>;
147 xlnx,rxmem = <0x800>;
149 phy-handle = <&phy0>;
152 #address-cells = <1>;
154 phy0: ethernet-phy@1 {
155 device_type = "ethernet-phy";
162 axi_ethernet_eth1: ethernet@40000000 {
163 compatible = "xlnx,axi-ethernet-1.00.a";
165 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
166 clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
168 reg = <0x00 0x40000000 0x00 0x40000>;
170 xlnx,rxmem = <0x800>;
172 phy-handle = <&phy1>;
173 axistream-connected = <&dma>;
176 #address-cells = <1>;
178 phy1: ethernet-phy@1 {
179 device_type = "ethernet-phy";