1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
17 (two external) and provides Ethernet packet communication and switching.
19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
21 and one RX channels and operating by NAVSS Unified DMA Peripheral Root
22 Complex (UDMA-P) controller.
25 updated Address Lookup Engine (ALE).
26 priority level Quality Of Service (QOS) support (802.1p)
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
28 Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
29 Flow Control (802.3x) Support
30 Time Sensitive Network Support
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
32 IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
33 Configurable number of addresses plus VLANs
34 Configurable number of classifier/policers
35 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
36 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
38 Management Data Input/Output (MDIO) interface for PHYs management
39 RMII/RGMII Interfaces support
40 new version of Common Platform Time Sync (CPTS)
42 The CPSWxG NUSS is integrated into
43 device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
44 device MAIN domain named CPSW0 on AM642x SoC.
46 Specifications can be found at
47 https://www.ti.com/lit/pdf/spruid7
48 https://www.ti.com/lit/zip/spruil1
49 https://www.ti.com/lit/pdf/spruim2
52 "#address-cells": true
59 - ti,j7200-cpswxg-nuss
61 - ti,j721e-cpswxg-nuss
62 - ti,j784s4-cpswxg-nuss
67 The physical base address and size of full the CPSWxG NUSS IO range
79 description: CPSWxG NUSS functional clock
85 assigned-clock-parents: true
118 description: CPSWxG NUSS external ports
120 $ref: ethernet-controller.yaml#
121 unevaluatedProperties: false
127 description: CPSW port number
132 - description: CPSW MAC's PHY.
133 - description: Serdes PHY. Serdes PHY is required only if
134 the Serdes has to be configured in the
135 Single-Link configuration.
144 description: label associated with this port
147 $ref: /schemas/types.yaml#/definitions/flag
149 Specifies the port works in mac-only mode.
152 $ref: /schemas/types.yaml#/definitions/phandle-array
155 - description: Phandle to the system control device node which
156 provides access to efuse
157 - description: offset to efuse registers???
159 Phandle to the system control device node which provides access
160 to efuse IO range with MAC addresses
166 additionalProperties: false
171 $ref: ti,davinci-mdio.yaml#
178 $ref: ti,k3-am654-cpts.yaml#
180 CPSW Common Platform Time Sync (CPTS) module.
202 - ti,j721e-cpswxg-nuss
203 - ti,j784s4-cpswxg-nuss
208 "^port@[5-8]$": false
221 - ti,j7200-cpswxg-nuss
222 - ti,j721e-cpswxg-nuss
223 - ti,j784s4-cpswxg-nuss
228 "^port@[3-8]$": false
235 additionalProperties: false
239 #include <dt-bindings/soc/ti,sci_pm_domain.h>
240 #include <dt-bindings/net/ti-dp83867.h>
241 #include <dt-bindings/interrupt-controller/irq.h>
242 #include <dt-bindings/interrupt-controller/arm-gic.h>
245 #address-cells = <2>;
248 mcu_cpsw: ethernet@46000000 {
249 compatible = "ti,am654-cpsw-nuss";
250 #address-cells = <2>;
252 reg = <0x0 0x46000000 0x0 0x200000>;
253 reg-names = "cpsw_nuss";
254 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
256 clocks = <&k3_clks 5 10>;
258 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
262 dmas = <&mcu_udmap 0xf000>,
271 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
275 #address-cells = <1>;
282 ti,syscon-efuse = <&mcu_conf 0x200>;
283 phys = <&phy_gmii_sel 1>;
285 phy-mode = "rgmii-rxid";
286 phy-handle = <&phy0>;
290 davinci_mdio: mdio@f00 {
291 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
292 reg = <0x0 0xf00 0x0 0x100>;
293 #address-cells = <1>;
295 clocks = <&k3_clks 5 10>;
297 bus_freq = <1000000>;
299 phy0: ethernet-phy@0 {
301 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
302 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
308 compatible = "ti,am65-cpts";
309 reg = <0x0 0x3d000 0x0 0x400>;
310 clocks = <&k3_clks 18 2>;
311 clock-names = "cpts";
312 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-names = "cpts";
314 ti,cpts-ext-ts-inputs = <4>;
315 ti,cpts-periodic-outputs = <2>;