1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
17 (two external) and provides Ethernet packet communication and switching.
19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
21 and one RX channels and operating by NAVSS Unified DMA Peripheral Root
22 Complex (UDMA-P) controller.
25 updated Address Lookup Engine (ALE).
26 priority level Quality Of Service (QOS) support (802.1p)
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
28 Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
29 Flow Control (802.3x) Support
30 Time Sensitive Network Support
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
32 IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
33 Configurable number of addresses plus VLANs
34 Configurable number of classifier/policers
35 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
36 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
38 Management Data Input/Output (MDIO) interface for PHYs management
39 RMII/RGMII Interfaces support
40 new version of Common Platform Time Sync (CPTS)
42 The CPSWxG NUSS is integrated into
43 device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
44 device MAIN domain named CPSW0 on AM642x SoC.
46 Specifications can be found at
47 https://www.ti.com/lit/pdf/spruid7
48 https://www.ti.com/lit/zip/spruil1
49 https://www.ti.com/lit/pdf/spruim2
52 "#address-cells": true
64 The physical base address and size of full the CPSWxG NUSS IO range
76 description: CPSWxG NUSS functional clock
82 assigned-clock-parents: true
115 description: CPSWxG NUSS external ports
117 $ref: ethernet-controller.yaml#
123 description: CPSW port number
127 description: phandle on phy-gmii-sel PHY
130 description: label associated with this port
133 $ref: /schemas/types.yaml#/definitions/flag
135 Specifies the port works in mac-only mode.
138 $ref: /schemas/types.yaml#/definitions/phandle-array
141 - description: Phandle to the system control device node which
142 provides access to efuse
143 - description: offset to efuse registers???
145 Phandle to the system control device node which provides access
146 to efuse IO range with MAC addresses
152 additionalProperties: false
157 $ref: "ti,davinci-mdio.yaml#"
164 $ref: "ti,k3-am654-cpts.yaml#"
166 CPSW Common Platform Time Sync (CPTS) module.
181 additionalProperties: false
185 #include <dt-bindings/pinctrl/k3.h>
186 #include <dt-bindings/soc/ti,sci_pm_domain.h>
187 #include <dt-bindings/net/ti-dp83867.h>
188 #include <dt-bindings/interrupt-controller/irq.h>
189 #include <dt-bindings/interrupt-controller/arm-gic.h>
192 #address-cells = <2>;
195 mcu_cpsw: ethernet@46000000 {
196 compatible = "ti,am654-cpsw-nuss";
197 #address-cells = <2>;
199 reg = <0x0 0x46000000 0x0 0x200000>;
200 reg-names = "cpsw_nuss";
201 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
203 clocks = <&k3_clks 5 10>;
205 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
209 dmas = <&mcu_udmap 0xf000>,
218 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
222 #address-cells = <1>;
229 ti,syscon-efuse = <&mcu_conf 0x200>;
230 phys = <&phy_gmii_sel 1>;
232 phy-mode = "rgmii-rxid";
233 phy-handle = <&phy0>;
237 davinci_mdio: mdio@f00 {
238 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
239 reg = <0x0 0xf00 0x0 0x100>;
240 #address-cells = <1>;
242 clocks = <&k3_clks 5 10>;
244 bus_freq = <1000000>;
246 phy0: ethernet-phy@0 {
248 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
249 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
255 compatible = "ti,am65-cpts";
256 reg = <0x0 0x3d000 0x0 0x400>;
257 clocks = <&k3_clks 18 2>;
258 clock-names = "cpts";
259 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
260 interrupt-names = "cpts";
261 ti,cpts-ext-ts-inputs = <4>;
262 ti,cpts-periodic-outputs = <2>;