1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments ICSSG PRUSS Ethernet
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
14 Communication Subsystem.
17 - $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
22 - ti,am642-icssg-prueth # for AM64x SoC family
23 - ti,am654-icssg-prueth # for AM65x SoC family
26 $ref: /schemas/types.yaml#/definitions/phandle
28 phandle to MSMC SRAM node
47 $ref: /schemas/types.yaml#/definitions/phandle
49 phandle to MII_G_RT module's syscon regmap.
52 $ref: /schemas/types.yaml#/definitions/phandle
54 phandle to MII_RT module's syscon regmap
57 $ref: /schemas/types.yaml#/definitions/phandle-array
62 phandle to IEP (Industrial Ethernet Peripheral) for ICSSG
67 Interrupt specifiers to TX timestamp IRQ.
76 additionalProperties: false
87 description: ICSSG PRUETH external ports
88 $ref: ethernet-controller.yaml#
89 unevaluatedProperties: false
95 description: ICSSG PRUETH port number
100 ti,syscon-rgmii-delay:
103 - description: phandle to system controller node
104 - description: The offset to ICSSG control register
105 $ref: /schemas/types.yaml#/definitions/phandle-array
107 phandle to system controller node and register offset
108 to ICSSG control register for RGMII transmit delay
110 ti,half-duplex-capable:
113 Indicates that the PHY output pin COL is routed to ICSSG GPIO pin
114 (PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is
115 capable of half duplex operations.
135 unevaluatedProperties: false
139 /* Example k3-am654 base board SR2.0, dual-emac */
140 pruss2_eth: ethernet {
141 compatible = "ti,am654-icssg-prueth";
142 pinctrl-names = "default";
143 pinctrl-0 = <&icssg2_rgmii_pins_default>;
146 ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
147 <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
148 firmware-name = "/*(DEBLOBBED)*/",
154 ti,pruss-gp-mux-sel = <2>, /* MII mode */
160 dmas = <&main_udmap 0xc300>, /* egress slice 0 */
161 <&main_udmap 0xc301>, /* egress slice 0 */
162 <&main_udmap 0xc302>, /* egress slice 0 */
163 <&main_udmap 0xc303>, /* egress slice 0 */
164 <&main_udmap 0xc304>, /* egress slice 1 */
165 <&main_udmap 0xc305>, /* egress slice 1 */
166 <&main_udmap 0xc306>, /* egress slice 1 */
167 <&main_udmap 0xc307>, /* egress slice 1 */
168 <&main_udmap 0x4300>, /* ingress slice 0 */
169 <&main_udmap 0x4301>; /* ingress slice 1 */
170 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
171 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
173 ti,mii-g-rt = <&icssg2_mii_g_rt>;
174 ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
175 interrupt-parent = <&icssg2_intc>;
176 interrupts = <24 0 2>, <25 1 3>;
177 interrupt-names = "tx_ts0", "tx_ts1";
179 #address-cells = <1>;
181 pruss2_emac0: port@0 {
183 phy-handle = <&pruss2_eth0_phy>;
184 phy-mode = "rgmii-id";
185 interrupts-extended = <&icssg2_intc 24>;
186 ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
187 /* Filled in by bootloader */
188 local-mac-address = [00 00 00 00 00 00];
191 pruss2_emac1: port@1 {
193 phy-handle = <&pruss2_eth1_phy>;
194 phy-mode = "rgmii-id";
195 interrupts-extended = <&icssg2_intc 25>;
196 ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
197 /* Filled in by bootloader */
198 local-mac-address = [00 00 00 00 00 00];