1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI SoC Ethernet Switch Controller (CPSW)
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an ethernet switch. It provides the
16 gigabit media independent interface (GMII),reduced gigabit media
17 independent interface (RGMII), reduced media independent interface (RMII),
18 the management data input output (MDIO) for physical layer device (PHY)
24 - const: ti,cpsw-switch
26 - const: ti,am335x-cpsw-switch
27 - const: ti,cpsw-switch
29 - const: ti,am4372-cpsw-switch
30 - const: ti,cpsw-switch
32 - const: ti,dra7-cpsw-switch
33 - const: ti,cpsw-switch
38 The physical base address and size of full the CPSW module IO range
50 description: CPSW functional clock
58 - description: RX_THRESH interrupt
59 - description: RX interrupt
60 - description: TX interrupt
61 - description: MISC interrupt
73 $ref: /schemas/types.yaml#/definitions/phandle
75 Phandle to the system control device node which provides access to
76 efuse IO range with MAC addresses
80 additionalProperties: false
91 description: CPSW external ports
93 $ref: ethernet-controller.yaml#
94 unevaluatedProperties: false
100 description: CPSW port number
104 description: phandle on phy-gmii-sel PHY
107 description: label associated with this port
110 $ref: /schemas/types.yaml#/definitions/uint32
114 Specifies default PORT VID to be used to segregate
115 ports. Default value - CPSW port number.
123 unevaluatedProperties: false
125 The Common Platform Time Sync (CPTS) module
130 description: CPTS reference clock
137 $ref: /schemas/types.yaml#/definitions/uint32
139 Numerator to convert input clock ticks into ns
142 $ref: /schemas/types.yaml#/definitions/uint32
144 Denominator to convert input clock ticks into ns.
145 Mult and shift will be calculated basing on CPTS rftclk frequency if
146 both cpts_clock_shift and cpts_clock_mult properties are not provided.
157 $ref: "ti,davinci-mdio.yaml#"
171 additionalProperties: false
175 #include <dt-bindings/interrupt-controller/irq.h>
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/clock/dra7.h>
180 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
182 ranges = <0 0 0x4000>;
183 clocks = <&gmac_main_clk>;
185 #address-cells = <1>;
187 syscon = <&scm_conf>;
189 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
193 interrupt-names = "rx_thresh", "rx", "tx", "misc";
196 #address-cells = <1>;
202 mac-address = [ 00 00 00 00 00 00 ];
203 phys = <&phy_gmii_sel 1>;
204 phy-handle = <ðphy0_sw>;
206 ti,dual-emac-pvid = <1>;
212 mac-address = [ 00 00 00 00 00 00 ];
213 phys = <&phy_gmii_sel 2>;
214 phy-handle = <ðphy1_sw>;
216 ti,dual-emac-pvid = <2>;
220 davinci_mdio_sw: mdio@1000 {
221 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
222 reg = <0x1000 0x100>;
223 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
225 #address-cells = <1>;
227 bus_freq = <1000000>;
229 ethphy0_sw: ethernet-phy@0 {
233 ethphy1_sw: ethernet-phy@1 {
239 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
240 clock-names = "cpts";